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"A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology."
Rong-Jyi Yang, Shen-Iuan Liu (2007)
- Rong-Jyi Yang, Shen-Iuan Liu:
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology. IEEE J. Solid State Circuits 42(11): 2338-2347 (2007)
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