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28th PACT 2019: Seattle, WA, USA
- 28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019, Seattle, WA, USA, September 23-26, 2019. IEEE 2019, ISBN 978-1-7281-3613-4
Session 1: Best-Papers
- Udit Gupta
, Brandon Reagen, Lillian Pentecost
MASR: A Modular Accelerator for Sparse RNNs. 1-14 - Roshan Dathathri, Gurbinder Gill, Loc Hoang, Vishwesh Jatala, Keshav Pingali, V. Krishna Nandivada, Hoang-Vu Dang, Marc Snir:
Gluon-Async: A Bulk-Asynchronous System for Distributed and Heterogeneous Graph Analytics. 15-28 - Shintaro Iwasaki
BOLT: Optimizing OpenMP Parallel Regions with User-Level Threads. 29-42 - Daniel Townley, Dmitry Ponomarev:
SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors. 43-54
Session 2A: Compiler Optimization and Code Generation 1
- Bruce Collie
Type-Directed Program Synthesis and Constraint Generation for Library Portability. 55-67 - Apala Guha, Naveen Vedula, Arrvindh Shriraman:
Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators. 68-81 - Patrick Nappa, David Zhao
Fast Parallel Equivalence Relations in a Datalog Compiler. 82-96
Session 2B: Memory/Storage Systems 1
- Jongwook Chung, Yuhwan Ro, Joonsung Kim, Jaehyung Ahn, Jangwoo Kim, John Kim
Enforcing Last-Level Cache Partitioning through Memory Virtual Channels. 97-109 - Richard Afoakwa, Lejie Lu, Hui Wu, Michael C. Huang
To Stack or Not To Stack. 110-123 - Soklong Lim, Zaixin Lu, Bin Ren, Xuechen Zhang:
Enforcing Crash Consistency of Evolving Network Analytics in Non-Volatile Main Memory Systems. 124-137
Session 3A: Hardware/Software for Security
- Biswabandan Panda:
Fooling the Sense of Cross-Core Last-Level Cache Eviction Based Attacker by Prefetching Common Sense. 138-150 - Kristin Barber, Anys Bacha, Li Zhou, Yinqian Zhang, Radu Teodorescu:
SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels. 151-164
Session 3B: Hardware/Software for Machine Learning
- Myeonggyun Han, Jihoon Hyun, Seongbeom Park, Jinsu Park, Woongki Baek:
MOSAIC: Heterogeneity-, Communication-, and Constraint-Aware Model Slicing and Execution for Accurate and Efficient Inference. 165-177 - Xiao Dong
Acorns: A Framework for Accelerating Deep Neural Networks with Input Sparsity. 178-191
Session 4A: Concurrency Management
- Sunjae Park, Christopher J. Hughes
Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory. 192-204 - Naama Ben-David, Ziv Scully
Unfair Scheduling Patterns in NUMA Architectures. 205-218 - Pantea Zardoshti, Tingzhe Zhou, Yujie Liu, Michael F. Spear
Optimizing Persistent Memory Transactions. 219-231
Session 4B: Heterogeneous Systems and Accelerators 1
- Daniel Castro
HeTM: Transactional Memory for Heterogeneous Systems. 232-244 - Amir Watad, Alexander Libov, Ohad Shacham, Edward Bortnikov, Mark Silberstein:
Achieving Scalability in a k-NN Multi-GPU Network Service with Centaur. 245-257 - Mohamed Assem Ibrahim
Analyzing and Leveraging Remote-Core Bandwidth for Enhanced Performance in GPUs. 258-271
Session 5A: Domain/Application-Specific Hardware/Software
- Lewis Crawford, Michael F. P. O'Boyle:
Specialization Opportunities in Graphical Workloads. 272-283 - Farzaneh Zokaee, Mingzhe Zhang, Lei Jiang:
FindeR: Accelerating FM-Index-Based Exact Pattern Matching in Genomic Sequences through ReRAM Technology. 284-295 - Yan Pei, Swarnendu Biswas, Donald S. Fussell, Keshav Pingali:
SLAMBooster: An Application-Aware Online Controller for Approximation in Dense SLAM. 296-310
Session 5B: Heterogeneous Systems and Accelerators 2
- Zhen Lin
Exploring Memory Persistency Models for GPUs. 311-323 - Ahmed E. Helal, Ashwin M. Aji, Michael L. Chu, Bradford M. Beckmann, Wu-chun Feng:
Adaptive Task Aggregation for High-Performance Sparse Solvers on GPUs. 324-336 - Tayler Hicklin Hetherington, Maria Lubeznov, Deval Shah, Tor M. Aamodt:
EDGE: Event-Driven GPU Execution. 337-353
Session 6A: Compiler Optimization and Code Generation 2
- Ari Rasch, Richard Schulze, Sergei Gorlatch:
Generating Portable High-Performance Code via Multi-Dimensional Homomorphisms. 354-369 - Tobias Gysi, Tobias Grosser
Absinthe: Learning an Analytical Performance Model to Fuse and Tile Stencil Codes in One Shot. 370-382
Session 6B: Memory/Storage Systems 2
- Jiajun Wang, Prakash Ramrakhyani, Wendy Elsasser
Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all? 383-394 - Ziqi Wang
Multiversioned Page Overlays: Enabling Faster Serializable Hardware Transactional Memory. 395-408
Session 7: Parallel Algorithms and Applications
- Zhenghai Chen, Tiow Seng Tan:
Computing Three-Dimensional Constrained Delaunay Refinement Using the GPU. 409-420 - Jesun Sahariar Firoz, Marcin Zalewski, Andrew Lumsdaine
A Synchronization-Avoiding Distance-1 Grundy Coloring Algorithm for Power-Law Graphs. 421-432 - Giovanni Balduzzi, Arghya Chatterjee
Accelerating DCA++ (Dynamical Cluster Approximation) Scientific Application on the Summit Supercomputer. 433-444 - Gangyi Zhu, Peng Jiang
A Methodology for Characterizing Sparse Datasets and Its Application to SIMD Performance Prediction. 445-456
Posters
- Ningxin Zheng, Quan Chen, Yong Yang, Jin Li, Wenli Zheng, Minyi Guo:
POSTER: Precise Capacity Planning for Database Public Clouds. 457-458 - Roman Kaplan, Leonid Yavits, Ran Ginosar:
POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. 459-460 - Jinsu Park, Seongbeom Park, Myeonggyun Han, Woongki Baek:
POSTER: The Performance Impact of Thread Packing on Synchronization-Intensive Applications. 461-462 - Reza Yazdani, José-María Arnau, Antonio González:
POSTER: Leveraging Run-Time Feedback for Efficient ASR Acceleration. 463-464 - Charles Jin, Muthu Manikandan Baskaran, Benoît Meister:
POSTER: Automatic Parallelization Targeting Asynchronous Task-Based Runtimes. 465-466 - Xi Wang, Jie Li, Antonino Tumeo, John D. Leidel, Yong Chen:
POSTER: Memory Hotspot Optimization for Data-Intensive Applications. 467-468 - Jungwoo Choi, Boyeal Kim, Ji-Ye Jeon, Hyuk-Jae Lee, Euicheol Lim, Chae-Eun Rhee:
POSTER: GPU Based Near Data Processing for Image Processing with Pattern Aware Data Allocation and Prefetching. 469-470 - Sayantan Ray, Madhu Mutyam:
POSTER: Variable Sized Cache-Block Compaction. 471-472 - Priyank Faldu
POSTER: Domain-Specialized Cache Management for Graph Analytics. 473-474 - Abdullah Khalufa, Graham D. Riley, Mikel Luján:
POSTER: Runtime Adaptations for Energy-Efficient VSLAM. 475-476 - Leonid Yavits, Roman Kaplan, Ran Ginosar:
POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework. 477-478 - Adrián Barredo
POSTER: An Optimized Predication Execution for SIMD Extensions. 479-480 - Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter:
POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. 481-482 - Adrián Barredo
POSTER: SPiDRE: Accelerating Sparse Memory Access Patterns. 483-484 - Hyojin Sung, Tong Chen, Alexandre E. Eichenberger, Kevin K. O'Brien:
POSTER: CogR: Exploiting Program Structures for Machine-Learning Based Runtime Solutions. 485-486 - Teng Yu, Pavlos Petoumenos
POSTER: A Collaborative Multi-Factor Scheduler for Asymmetric Multicore Processors. 487-488 - Yuan Wen, Andrew Anderson, Valentin Radu
POSTER: Space and Time Optimal DNN Primitive Selection with Integer Linear Programming. 489-490 - Zhenwei Wu, Kai Lu, Wenzhe Zhang, Andrew Nisbet
POSTER: Quiescent and Versioned Shadow Copies for NVM. 491-492 - Satoshi Imamura
POSTER: AR-MMAP: Write Performance Improvement of Memory-Mapped File. 493-494 - Masab Ahmad, Mohsin Shan, Akif Rehman, Omer Khan:
POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms. 495-496 - Mengchi Zhang
POSTER: Quantifying the Direct Overhead of Virtual Function Calls on Massively Parallel Architectures. 497-498 - Eddie C. Davis, Catherine Olschanowsky:
POSTER: A Polyhedral+Dataflow Intermediate Language for Performance Exploration. 499-500 - Babak Zamirai, Salar Latifi, Scott A. Mahlke:
POSTER: Pairing Up CNNs for High Throughput Deep Learning. 501-502 - Xiaojia Song, Tao Xie, Stephen Fischer:
POSTER: A Memory-Access-Efficient Adaptive Implementation of kNN on FPGA through HLS. 503-504
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