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NANOARCH 2010: Anaheim, CA, USA
- Shamik Das, Iris Bahar, Michael T. Niemier:
2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-8020-3 - Robinson E. Pino, James W. Bohl, Nathan R. McDonald, Bryant T. Wysocki, Peter J. Rozwood, Kristy A. Campbell, Antonio S. Oblea, Achyut Timilsina:
Compact method for modeling and simulation of memristor devices: Ion conductor chalcogenide-based memristor devices. 1-4 - Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose:
Memristor based programmable threshold logic array. 5-10 - Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, Csaba Andras Moritz:
Towards logic functions as the device. 11-16 - Marco Ottavi, Salvatore Pontarelli, Erik DeBenedictis, Adelio Salsano, Peter M. Kogge, Fabrizio Lombardi:
High throughput and low power dissipation in QCA pipelines using Bennett clocking. 17-22 - Shigeru Yamashita, Igor L. Markov:
Fast equivalence-checking for quantum circuits. 23-28 - Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier:
Design and comparison of NML systolic architectures. 29-34 - Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Jiang Xu:
UNION: A unified inter/intra-chip optical network for chip multiprocessors. 35-40 - Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha:
Fault modeling for FinFET circuits. 41-46 - Kotb Jabeur, David Navarro, Ian O'Connor, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy:
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs. 47-52 - Muzaffer O. Simsir, Niraj K. Jha:
NanoV: Nanowire-based VLSI design. 53-58 - Eric Rachlin, John E. Savage:
Stochastic nanoscale addressing for logic. 59-64 - Michele De Marchi, M. Haykel Ben Jamaa, Giovanni De Micheli:
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications. 65-70 - Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra:
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes. 71-76 - Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, H.-S. Philip Wong:
Intel LVS logic as a combinational logic paradigm in CNT technology. 77-81
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