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5. IWSOC 2005: Banff, Alberta, Canada
- Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada. IEEE Computer Society 2005, ISBN 0-7695-2403-6
Introduction
- Introduction.
Plenary
- Juan Antonio Carballo:
Open HW, Open Design SW, and the VC Ecosystem Dilemma. 3-6
Semiconductor Technologies
- Paul Kempf:
Enabling Technology for Analog Integration, invited. 9 - Sorin P. Voinigescu, Michael Gordon, Chihou Lee, Terry Yao, Alain M. Mangan, Kenneth H. K. Yau:
System-on-Chip Design beyond 50 GHz, invited. 10-13 - Scott E. Thompson:
Strained Si and the Future Direction of CMOS, invited. 14-16
Software/Hardware System Co-design
- Johan van der Tang, Harm van Rumpt, Dieter Kasperkovitz:
HW/SW Co-Design for SoC on Mobile Platforms, invited. 19-23 - Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois:
A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction. 24-29 - Paul R. Schumacher, Marco Mattavelli, Adrian Chirila-Rus, Robert D. Turney:
A Software/Hardware Platform for Rapid Prototyping of Video and Multimedia Designs. 30-33 - Baodong Yu, Xuecheng Zou:
The Software/Hardware Co-Debug Environment with Emulator. 34-38
Manufacturing & Reliability
- Artur Balasinski:
DfM for SoC, invited. 41-46 - Yoon Huh, Peter Bendix, Kyungjin Min, Jau-Wen Chen, Ravindra Narayan, Larry D. Johnson, Steven H. Voldman:
ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited. 47-53 - Azzouz Nezar, Michael Creighton:
System on Chip: Challenges and Design for Manufacturing, invited. 54-59 - Mohab Anis, Mohamed H. Abu-Rahma:
Leakage Current Variability in Nanometer Technologies, invited. 60-63 - Nur Kurt-Karsilayan:
Generic Modeling of Non-planar Dielectrics for 2 1/2D Parasitic Extraction. 64-69
Memories for SoC
- Luca Larcher
, Paolo Pavan
Flash Memories for SoC: An Overview on System Constraints and Technology Issues, invited. 73-77 - Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang:
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits. 78-81
Analog and Mixed-Signal IC Design
- Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski:
PLL-Based Fractional-N Frequency Synthesizers. 85-91 - M. M. Tabriz, Nasser Masoumi:
A New Topology for Power Control of High Efficiency Class-E Switched Mode Power Amplifier. 92-95 - Joshua K. Nakaska, James W. Haslett:
A CMOS Quality Factor Enhanced Parallel Resonant LC-Tank with Independent Q and Frequency Tuning for RF Integrated Filters. 96-100 - Hyoungsoo Kim, Youngsik Hur, Moonkyun Maeng, Franklin Bien, Soumya Chandramouli, Edward Gebara, Joy Laskar:
A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling. 101-106 - Shih-Chang Hsia, Wen-Ching Lee:
A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit. 107-110 - Chia-Jung Chang, Ke-Horng Chen
Bidirectional Current-Mode Capacitor Multiplier in DC-DC Converter Compensation. 111-116 - Chun-Yueh Huang, Tsung-Tien Hou, Chi-Chieh Chuang, Hung-Yu Wang:
Design of 12-bit 100-MHz Current-Steering DAC for SoC Applications. 117-122 - Syed Masood Ali, Rabin Raut, Mohamad Sawan:
A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture. 123-126 - Bahar Khadem Hosseinieh, Nasser Masoumi:
A Comprehensive Model for On-Chip Spiral Inductors. 127-131 - Kenneth A. Townsend, James W. Haslett, Krzysztof Iniewski:
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits. 132-136
Digital System Design for SoC
- Lech Józwiak:
Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited. 139-142 - James B. Kuo:
Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited. 143-148 - Charles E. Berndt, Tad A. Kwasniewski:
A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane. 149-153 - Robert Bogdan Staszewski
Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude Conversion. 154-159 - Xiaolong Yuan, Andreas Gothenberg
Improved Wideband Low Distortion Cascaded Delta-Sigma Modulator. 160-164
Sensors
- Mohammad Hadi Izadi, Karim S. Karim:
Noise Analysis of a CMOS Active Pixel Sensor for Tomographic Mammography. 167-171 - Amine Bermak
Conversion Time Analysis of Time Domain Digital Pixel Sensor in Uniform and Non-Uniform Quantizers, invited. 172-175 - Yanjie Wang, Yanbin Wang, Garry Tarr, Kris Iniewski:
A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH Extractor. 176-179 - Haigang Yang, Hongguang Sun, Jinghong Han, Jinbao Wei, Zengjin Lin, Shanhong Xia, Hua Zhong:
A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology. 180-183 - Mohammad M. Ahmadi
A Very Low Power CMOS Potentiostat for Bioimplantable Applications. 184-189
Multimedia IP Cores
- Mostafa Borhani
An Acoustic Echo Canceller Chip. 193-198 - Shih-Chang Hsia, Shih Wen Chou:
A High-Performance Error Concealment Processor for Video Decoder. 199-202 - Farid Boussaïd
A Scalable Low Power Imager Architecture for Compound-Eye Vision Sensors. 203-206 - Choudhury A. Rahman, Wael M. Badawy
UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC. 207-210 - Ihab Amer, Choudhury A. Rahman, Tamer Mohamed, Mohammed Sayed, Wael M. Badawy
A Hardware-Accelerated Framework with IP-Blocks for Application in MPEG-4. 211-214
Wireless Systems
- Robert Bogdan Staszewski
Digital RF Processing Techniques for SoC Radios, invited. 217-222 - Christian Cojocaru:
Low Power Bluetooth for Headset Applications, invited. 223-226 - N. Patrick Kelly, Ben W. Jones, Nestor A. Fesas, John M. Morton:
Design of 802.11 Access Point Chipsets for Enterprise Applications, invited. 227-232 - Robert Bogdan Staszewski
VHDL Simulation and Modeling of an All-Digital RF Transmitter. 233-238 - Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park:
Efficient Pattern-Based Emulation for IEEE 802.11a Baseband. 239-242 - Yanjie Wang, Kris Iniewski:
A 2.3GHz CMOS Transimpedance Preamplifier for Optical Communication. 243-246 - Yanjie Wang, M. Zamin Khan, Kris Iniewski:
A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHz. 247-251 - Daniel Wiklund, Dake Liu:
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip. 252-256 - Jung Ko, Vincent C. Gaudet
A Tier 3 Software Defined AM Radio. 257-261
VLSI Physical Design
- S. A. Moghaddam, Nasser Masoumi, Caro Lucas:
A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance. 265-269 - Jianhua Li, Laleh Behjat
A Structure Based Clustering Algorithm with Applications to VLSI Physical Design. 270-274 - Pawoumodom L. Takouda, Miguel F. Anjos
Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization. 275-280
Towards SoC Design Automation Tools for SoC
- Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi
Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm. 283-288 - Robert Grou-Szabo, Hany Ghattas, Yvon Savaria, Gabriela Nicolescu:
Component-Based Methodology for Hardware Design of a Dataflow Processing Network. 289-294 - Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang:
An Automatic Layout Generator for I/O Cells. 295-300 - Tina Lindkvist:
Additional Knowledge of Bus Invert Coding Schemes. 301-303 - Marco Mattavelli, Massimo Ravasi:
High Level Extraction of SoC Architectural Information from Generic C Algorithmic Descriptions. 304-307 - Abhijit Ray, Thambipillai Srikanthan, Wu Jigang:
Practical Techniques for Performance Estimation of Processors. 308-311 - Blair Schiffner, Jianhua Li, Laleh Behjat
A Multivalue Eigenvalue Based Circuit Partitioning Technique. 312-316 - Haidar Harmanani
A Hybrid Distributed Test Generation Method Using Deterministic and Genetic Algorithms. 317-322 - Russell Klein, Tomasz Piekarz:
Accelerating Functional Simulation for Processor Based Designs, invited. 323-328 - Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park:
Instruction Based Testbench Architecture, invited. 329-333
Low-Power SoC
- J. Derakhshandeh, Nasser Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot:
A Precise Model for Leakage Power Estimation in VLSI Circuits. 337-340 - Moeed Israr, Tad A. Kwasniewski:
Turbo Codes - Digital IC Design. 341-346 - Eric Tell, Anders Nilsson, Dake Liu:
A Low Area and Low Power Programmable Baseband Processor Architecture. 347-351 - Hung-Ch Lee, Kuo-Tai Chang, Ke-Horng Chen
Power Saving of a Dynamic Width Controller for a Monolithic Current-Mode CMOS DC-DC Converter. 352-357 - Ki-Bog Kim, Chi-Ho Lin:
An Optimal ILP Model for Delay Time to Minimize Peak Power and Area. 358-362 - Meeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar:
Power Reduction Technique Using Multi-vt Libraries. 363-367 - Payam Ghafari, Ehsan Mirhadi, Mohab Anis, Shawki Areibi, Mohamed I. Elmasry:
A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets. 368-371 - Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su:
Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits. 372-375 - Richard F. Hobson, Scott Wakelin:
An Area-Efficient High-Speed AES S-Box Method. 376-379 - Sang-Ho Seo, Sin-Chong Park:
Low Latency and Power Efficient VD Using Register Exchanged State-Mapping Algorithm. 380-384
Digital IP Cores
- Amir Khatibzadeh, Kaamran Raahemifar:
A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier. 387-391 - Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen:
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process. 392-395 - Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy:
An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. 396-399 - Kyle Kelley, David Money Harris:
Very High Radix Scalable Montgomery Multipliers. 400-404 - Chul-hyung Ryu, Sung-Woong Ra:
A Fast Full Search Equivalent Encoding Algorithm for Image Vector Quantization Based on the WHT and a LUT. 405-409
Programmable and Reconfigurable Cores
- Paul E. Hasler:
Low-Power Programmable Signal Processing, invited. 413-418 - Mona Safar, M. Watheq El-Kharashi, Ashraf Salem
An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking. 419-424 - David N. Abramson, Jordan D. Gray, Shyam Subramanian, Paul E. Hasler:
A Field-Programmable Analog Array Using Translinear Elements. 425-428 - P. Samson, P. Sinha:
Hardware Acceleration of Deadlock Avoidance and Detection in Real-Time Operating Systems. 429-433 - Joachim Becker, Fabian Henrici, Yiannos Manoli:
System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array. 434-438 - Miro Milanovic
FPGA Implementation of Digital Controller for DC-DC Buck Converter. 439-443 - A. N. M. Ehtesham Rafiq, M. Watheq El-Kharashi, Fayez Gebali:
Systolic Array-Based String Matching Unit for Spam Blocking. 444-449 - Esam Khan, M. Watheq El-Kharashi, Fayez Gebali, Mostafa I. H. Abd-El-Barr:
An FPGA Design of a Unified Hash Engine for IPSec Authentication. 450-453 - Bill Pontikakis, François R. Boyer, Yvon Savaria:
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. 454-458 - Paul E. Hasler, AiChen Low:
Programmable Low Dropout Voltage Regulator. 459-462
Emerging Issue
- Earl E. Swartzlander Jr.:
Three Dimensional System on Chip Technology, invited. 465-470 - Sung-Rok Yoon, Sin-Chong Park:
Simulation and Analysis of Network on Chip Architecture for Wireless Communication System. 471-475 - Kenneth A. Townsend, James W. Haslett, Tommy Kwong-Kin Tsang, Mourad N. El-Gamal, Krzysztof Iniewski:
Recent Advances and Future Trends in Low Power Wireless Systems for Medical Applications. 476-481 - Paul E. Hasler:
Floating-Gate Devices, Circuits, and Systems, invited. 482-487
IP-Blocks for Broadband Networking
- Stephen Bates, Kris Iniewski:
10 GBPS over Copper Lines - State of the Art in VLSI, invited. 491-494 - Thomas Palkert:
A Review of Current Standards Activities for High Speed Physical Layers, invited. 495-499 - Miao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang:
Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications. 500-502 - S. M. Rezaul Hasan
A High Efficiency 3GHz 24-dBm CMOS Linear Power Amplifier for RF Application. 503-507 - Ching-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng:
A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications. 508-513 - Vladimir Stojanovic:
High-Speed Serial Links: Design Trends and Challenges, invited. 514
MPSOC
- Roger Su, Raman Mittal, Vivek Garg:
Synchronous Pipelined Relay Stations with Back-Pressure Tolerance. 517-520 - Xiqun Zhu, Yuan Ma:
Modular Architecture for System-on-Chip Design of Scalable MEMS Optical Switch Actuator Controller. 521-524 - Gyongsu Lee, Sin-Chong Park:
Architecture for Multi-processor SoC Platform Using Dedicated Channels. 525-529 - Sangik Choi, Shinwook Kang:
Implementation of an On-Chip Bus Bridge between Heterogeneous Buses with Different Clock Frequencies. 530-534 - Zhonghai Lu, Axel Jantsch:
Traffic Configuration for Evaluating Networks on Chips. 535-540 - Jin Lee, Sin-Chong Park:
Orthogonalized Communication Architecture for MP-SoC with Global Bus. 541-545 - Luiza Gheorghe, Gabriela Nicolescu:
MP SoCs Including Optical Interconnect. Technological Progresses and Challenges for CAD Tools Design. 546-551 - Seungbeom Lee, Sin-Chong Park:
Transaction Analysis of Multiprocessor Based Platform with Bus Matrix. 552-556 - Hung Tien Bui, Yvon Savaria:
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. 557-562
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