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17th IOLTS 2011: Athens, Greece
- 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece. IEEE Computer Society 2011, ISBN 978-1-4577-1053-7
- Seyab Khan, Said Hamdioui:
Modeling and mitigating NBTI in nanoscale circuits. 1-6 - Taiki Uemura, Takashi Kato
, Hideya Matsuyama, Keiji Takahisa, Mitsuhiro Fukuda, Kichiji Hatanaka:
Investigation of multi cell upset in sequential logic and validity of redundancy technique. 7-12 - Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara:
High-level synthesis for multi-cycle transient fault tolerant datapaths. 13-18 - Dhiego Silva, Letícia Maria Veiras Bolzani, Fabian Vargas:
An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems. 19-24 - Jaume Abella
RVC-based time-predictable faulty caches for safety-critical systems. 25-30 - Marco Paolieri, Riccardo Mariani:
Towards functional-safe timing-dependable real-time architectures. 31-36 - Ronaldo Rodrigues Ferreira, Álvaro Freitas Moreira, Luigi Carro
Matrix control-flow algorithm-based fault tolerance. 37-42 - Michael Augustin, Michael Gössel, Rolf Kraemer:
Selective fault tolerance for finite state machines. 43-48 - Enrico Costenaro, Massimo Violante, Dan Alexandrescu:
A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. 49-54 - Fabien Chaix, Gilles Bizot, Michael Nicolaidis, Nacer-Eddine Zergainoh:
Variability-aware task mapping strategies for many-cores processor chips. 55-60 - Rance Rodrigues, Sandip Kundu:
On graceful degradation of microprocessors in presence of faults via resource banking. 61-66 - Rance Rodrigues, Sandip Kundu:
On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units. 67-72 - Lilia Zaourar, Yann Kieffer, Arnaud Wenzel:
A multi-objective optimization for memory BIST sharing using a genetic algorithm. 73-78 - Aymen Fradi, Michael Nicolaidis, Lorena Anghel
Memory BIST with address programmability. 79-85 - Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
Generic BIST architecture for testing of content addressable memories. 86-91 - Cristiana Bolchini
A reliable fault classifier for dependable systems on SRAM-based FPGAs. 92-97 - Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner
An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. 98-103 - Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker
Estimation of component criticality in early design steps. 104-110 - Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González
New reliability mechanisms in memory design for sub-22nm technologies. 111-114 - Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas
A BIST scheme for testing and repair of multi-mode power switches. 115-120 - Rshdee Alhakim, Emmanuel Simeu, Kosai Raoof:
Internal model control for a self-tuning Delay-Locked Loop in UWB communication systems. 121-126 - Jayaram Natarajan, Shreyas Sen, Abhijit Chatterjee:
Real time cross-layer adaptation for minimum energy wireless image transport using bit error rate control. 127-132 - Ingrid Verbauwhede
The cost of cryptography: Is low budget possible? 133 - Paolo Maistri:
Countermeasures against fault attacks: The good, the bad, and the ugly. 134-137 - Berk Sunar:
Rise of the hardware Trojans. 138 - Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou
A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS. 139-144 - Aravind Rajendran, Yuriy Shiyanovskii, Frank Wolff, Christos A. Papachristou
Noise margin, critical charge and power-delay tradeoffs for SRAM design. 145-150 - Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. 151-156 - Kedar Karmarkar, Spyros Tragoudas:
Error correction encoding for multi-threshold capture mechanism. 157-162 - V. Prasanth
Reduced overhead soft error mitigation using error control coding techniques. 163-168 - Michael E. Imhof, Hans-Joachim Wunderlich:
Soft error correction in embedded storage elements. 169-174 - Dan Alexandrescu:
A comprehensive soft error analysis methodology for SoCs/ASICs memory instances. 175-176 - Gabriele Boschi, Riccardo Mariani, Stefano Lorenzini:
A verification strategy for fault-detection and fault-tolerance circuits. 177-178 - Anna Vaskova, Celia López-Ongil
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. 179-181 - Matthias Sauer, Victor Tomashevich, Jörg Müller, Matthew Lewis, Andreas Spilla, Ilia Polian, Bernd Becker
An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. 182-185 - Mikhail Baklashov:
An on-line memory state validation using shadow memory cloning. 186-189 - Navid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo
Control-flow error recovery using commodity multi-core architecture features. 190-191 - Osnat Keren, Ilya Levin
Detection of Trojan HW by using hidden information on the system. 192-193 - Eberhard Böhl, Paul Duplys:
Fault attack resistant deterministic random bit generator usable for key randomization. 194-195 - Ronak Salamat, Hamid R. Zarandi:
Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire. 196-197 - Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme:
Generalized parity-check matrices for SEC-DED codes with fixed parity. 198-201 - Jorge O. M. Esteves, Tiago H. Moita, Carlos B. Almeida
ICT: Interface software for the characterization and test of mixed-signal power cores. 202-205 - Cédric Killian, Camel Tanougast
Loopback output router for reliable Network on Chip. 206-207 - Luke Pierce, Spyros Tragoudas:
Multi-level secure JTAG architecture. 208-209 - Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov:
Self-checking test circuits for latches and flip-flops. 210-213 - Nahid Farhady Ghalaty, Mahdi Fazeli
Software-based control flow error detection and correction using branch triplication. 214-217 - Michael Linder, Alfred Eder, Klaus Oberländer, Martin Huch:
Variations of fault manifestation during Burn-In - A case study on industrial SRAM test results. 218-221 - Armin Krieg
A side channel attack countermeasure using system-on-chip power profile scrambling. 222-227 - Honorio Martín
AKARI-X: A pseudorandom number generator for secure lightweight systems. 228-233 - Zhen Wang, Mark G. Karpovsky:
Algebraic manipulation detection codes and their applications for design of secure cryptographic devices. 234-239 - Jaume Abella
Towards improved survivability in safety-critical systems. 240-245 - Taiga Takata, Yusuke Matsunaga:
A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. 246-251 - Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón
An analytical model for the calculation of the Expected Miss Ratio in faulty caches. 252-257 - Anna Vaskova, Celia López-Ongil
Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. 258-263 - Madalin Neagu
Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies. 264-269 - Paolo Bernardi
An effective methodology for on-line testing of embedded microprocessors. 270-275 - Rafal Baranowski, Hans-Joachim Wunderlich:
Fail-safety in core-based system design. 276-281
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