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ISSS 2000: Madrid, Spain
- Fadi J. Kurdahi, Román Hermida:
Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000. ACM / IEEE Computer Society 2000, ISBN 0-7695-0765-4
System Level Design Research in an Industrial Setting (Invited Talks)
- Warren Savage, John Chilton, Raul Camposano:
IP Reuse in the System on a Chip Era. 2-8 - Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh:
YAML: A Tool for Hardware Design Visualization and Capture. 9-17
New Frontiers for System-Level Power Management (Invited Talks)
- Yung-Hsiang Lu, Giovanni De Micheli, Luca Benini:
Requester-Aware Power Reduction. 18-24 - Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi:
Battery-Driven Dynamic Power Management of Portable Systems. 25-33
Code Generation and Scheduling
- Cagdas Akturan, Margarida F. Jacome:
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. 34-40 - F. Jesús Sánchez, Antonio González
:
Instruction Scheduling for Clustered VLIW Architectures. 41-46 - Natalino G. Busá, Albert van der Werf, Marco Bekooij:
Scheduling Coarse-Grain Operations for VLIW Processors. 47-54 - Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai:
Compiler Optimization on Instruction Scheduling for Low Power. 55-61
Embedded Tutorial
- Mateo Valero:
Architectures for One Billion of Transistors. 62
Panel: System Level Design - Solid Advances or Survival Strategies?
High Level and System Level Synthesis
- Apostolos A. Kountouris, Christophe Wolinski:
Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System. 66-72 - Olga Peñalba, José M. Mendías, María C. Molina:
Execution Condition Analysis in High Level Synthesis: A Unified Approach. 73-78 - Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha:
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design. 79-84 - Wander O. Cesário, Zoltan Sugar, Imed Moussa, Ahmed Amine Jerraya:
Efficient Integration of Behavioral Synthesis with Existing Design Flows. 85-90 - Neal K. Bambha, Shuvra S. Bhattacharyya:
A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems using a Period Graph Construct. 91-99
Reconfigurable Computing and Embedded Systems
- Juanjo Noguera, Rosa M. Badia
Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures. 100-106 - Rafael Maestre
Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. 107-114 - Tanja Van Achteren
Systematic Data Reuse Exploration Methodology for Irregular Access Patterns. 115-122 - Martin Grajcar:
Conditional Scheduling for Embedded Systems using Genetic List Scheduling. 123-129
System Level Modeling and Verification
- Fabian Wolf, Rolf Ernst:
Intervals in Software Execution Cost Analysis. 130-136 - Marek Jersak, Ying Cai, Dirk Ziegenbein, Rolf Ernst:
A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model. 137-142 - Matthias Meerwein, C. Baumgartner, T. Wieja, Wolfram Glauert:
Embedded Systems Verification with FPGA-Enhanced In-Circuit Emulator. 143-148 - Luis Alejandro Cortés, Petru Eles, Zebo Peng:
Verification of Embedded Systems using a Petri Net based Representation. 149-156 - Annette Muth, Georg Färber:
SDL as a System Level Specification Language for Application-Specific Hardware in a Rapid Prototyping Environment. 157-162 - Tony Givargis, Frank Vahid, Jörg Henkel:
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores. 163-171
Embedded Tutorial
- Wolfgang Rosenstiel:
Embedded Java. 172 - Rainer Leupers:
Code Generation for Embedded Processors. 173-179
High-Level Power Estimation (Invited Talks)
- Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel:
Lower Bound Estimation for Low Power High-Level Synthesis. 180-186 - Carlo Brandolese, William Fornaciari
A Multi-Level Strategy for Software Power Estimation. 187-192 - Tajana Simunic, Giovanni De Micheli, Luca Benini, Mat Hans:
Source Code Optimization and Profiling of Energy Consumption in Embedded Systems. 193-199
System Design Methodologies and Experiences
- Erik Brockmeyer, Arnout Vandecappelle, Sven Wuytack, Francky Catthoor:
Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs. 200-206 - Jeffrey Kang, Albert van der Werf, Paul E. R. Lippens:
Mapping Array Communication onto FIFO Communication - Towards an Implementation. 207-214 - Chanik Park, Soonhoi Ha:
Hardware Synthesis from SPDF Representation for Multimedia Applications. 215-220 - Roman L. Lysecky, Frank Vahid, Tony Givargis:
Experiments with the Peripheral Virtual Component Interface. 221-224 - Rafael Gadea Gironés
Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. 225-230
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