default search action
ISPASS 2024: Indianapolis, IN, USA
- IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2024, Indianapolis, IN, USA, May 5-7, 2024. IEEE 2024, ISBN 979-8-3503-7638-8
- Wim Heirman, Stijn Eyerman:
Message from the Program Chairs; ISPASS 2024. xii-xiii - Timothy Rogers:
Message from the General Chair; ISPASS 2024. xi - Erick Carvajal Barboza, Mahesh Ketkar, Paul Gratz, Jiang Hu:
Aiding Microprocessor Performance Validation with Machine Learning. 1-9 - Tanner Andrulis, Joel S. Emer, Vivienne Sze:
CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool. 10-23 - Mohammadreza Rezvani, Ali Jahanshahi, Daniel Wong:
Characterizing In-Kernel Observability of Latency-Sensitive Request-Level Metrics with eBPF. 24-35 - Xinyu Li, Yanzhi Lan, Gen Niu, Feng Xue, Fuxin Zhang:
BTBench: A Benchmark for Comprehensive Binary Translation Performance Evaluation. 36-47 - Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff:
MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems. 48-60 - Negar Neda, Austin Ebel, Benedict Reynwar, Brandon Reagen:
CiFlow: Dataflow Analysis and Optimization of Key Switching for Homomorphic Encryption. 61-72 - Victor Kariofillis, Natalie Enright Jerger:
Workload Characterization of Commercial Mobile Benchmark Suites. 73-84 - Yonghong Yan, Kewei Yan, Anjia Wang:
RTune: Towards Automated and Coordinated Optimization of Computing and Computational Objectives of Parallel Iterative Applications. 85-95 - Abhishek Tyagi, Reiley Jeyapaul, Chuteng Zhou, Paul N. Whatmough, Yuhao Zhu:
Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator. 96-108 - Md Sami Ul Islam Sami, Jingbo Zhou, Sujan Kumar Saha, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SAP: Silicon Authentication Platform for System-on-Chip Supply Chain Vulnerabilities. 109-119 - Odysseas Chatzopoulos, Maria Trakosa, George Papadimitriou, Wing Shek Wong, Dimitris Gizopoulos:
SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs. 120-131 - Gabin Schieffer, Daniel Araújo de Medeiros, Jennifer Faj, Aniruddha Marathe, Ivy Peng:
On the Rise of AMD Matrix Cores: Performance, Power Efficiency, and Programmability. 132-143 - Puru Sharma, Gary Goh Yipeng, Bin Gao, Longshen Ou, Dehui Lin, Deepak Sharma, Djordje Jevdjic:
DNA Storage Toolkit: A Modular End-to-End DNA Data Storage Codec and Simulator. 144-155 - Davit Grigoryan, Yuan-Hsi Chou
, Tor M. Aamodt:
Zatel: Sample Complexity-Aware Scale-Model Simulation for Ray Tracing. 156-166 - Panagiotis Strikos, Ahsen Ejaz, Ioannis Sourdis:
BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling. 167-178 - Johnson Umeike
Userspace Networking in gem5. 179-191 - Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz:
Vision Transformer Computation and Resilience for Dynamic Inference. 192-204 - William Won, Saeed Rashidi, Sudarshan Srinivasan, Tushar Krishna:
LIBRA: Enabling Workload-Aware Multi-Dimensional Network Topology Optimization for Distributed Training of Large AI Models. 205-216 - Kailash Gogineni, Sai Santosh Dayapule, Juan Gómez-Luna, Karthikeya Gogineni, Peng Wei, Tian Lan, Mohammad Sadrosadati, Onur Mutlu, Guru Venkataramani:
SwiftRL: Towards Efficient Reinforcement Learning on Real Processing-In-Memory Systems. 217-229 - Sanyam Mehta, Anna Yue:
Forward to the Past: An Alternative to Hybrid CPU Design. 230-240 - Bagus Hanindhito, Bhavesh Patel, Lizy K. John:
Bandwidth Characterization of DeepSpeed on Distributed Large Language Model Training. 241-256 - Alicia Golden, Samuel Hsia, Fei Sun, Bilge Acun, Basil Hosmer, Yejin Lee, Zachary DeVito, Jeff Johnson, Gu-Yeon Wei, David Brooks, Carole-Jean Wu:
Generative AI Beyond LLMs: System Implications of Multi-Modal Generation. 257-267 - Zishen Wan, Che-Kai Liu, Hanchen Yang, Ritik Raj, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Ananda Samajdar, Yingyan Celine Lin, Tushar Krishna, Arijit Raychowdhury:
Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI. 268-279 - Chandra Irugalbandara, Ashish Mahendra, Roland Daynauth, Tharuka Kasthuri Arachchige, Jayanaka Dantanarayana, Krisztián Flautner, Lingjia Tang, Yiping Kang, Jason Mars:
Scaling Down to Scale Up: A Cost-Benefit Analysis of Replacing OpenAI's LLM with Open Source SLMs in Production. 280-291 - Divya Kiran Kadiyala, Saeed Rashidi, Taekyung Heo, Abhimanyu Bambhaniya, Tushar Krishna, Alexandros Daglis:
Leveraging Memory Expansion to Accelerate Large-Scale DL Training. 292-294 - Pranab Dash, Y. Charlie Hu, Abhilash Jindal:
APGPM: Automated PMC-Based Power Modeling Methodology for Modern Mobile GPUs. 295-297 - Umer Shahid, Ayesha Ahmad, Shanzay Wasim:
Gem5-Based Evaluation of CVA6 SoC: Insights into the Architectural Design. 298-300 - Abenezer Wudenhe, Yu-Chia Liu, Chris Chen, Hung-Wei Tseng:
Accel-Bench: Exploring the Potential of Programming Using Hardware-Accelerated Functions. 301-303 - Debpratim Adak, Hyokeun Lee, Ben Feinberg, Gwendolyn Voskuilen, Clayton Hughes, Huiyang Zhou, Amro Awad:
SEFsim: A Statistically-Guided Fast DRAM Simulator. 304-306 - Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar, Joel S. Emer, Vivienne Sze:
Architecture-Level Modeling of Photonic Deep Neural Network Accelerators. 307-309 - Joshua Suetterlein, Stephen J. Young, Jesun Firoz, Joseph B. Manzano, Ryan D. Friese, Nathan R. Tallent, Kevin J. Barker, Timothy Stavenger:
Automatic Extraction of Network Configurations for Realistic Simulation and Validation. 310-312 - Kaifeng Xu, Georgios Tziantzioulis, David Wentzlaff:
MindPalace: A Framework for Studying Microarchitecture Design of Function-as-a-Service. 313-315 - Nikitha Karman, Kevin Wei, Dylan Scott, Natheesan Ratnasegar, Oguzhan Canpolat, Hieu Mai, Michael Ferdman:
Infrastructure for Exploring SIMT Architecture in General-Purpose Processors. 316-318 - Adrian Zhao
Distributed Training of Neural Radiance Fields: A Performance Characterization. 319-321 - Shubhendra Pal Singhal, Akihiro Hayashi, Vivek Sarkar:
Bottleneck Scenarios in Use of the Conveyors Message Aggregation Library. 322-324 - Andreas Abel, Yuying Li, Richard O'Grady, Chris Kennelly, Darryl Gove:
A Profiling-Based Benchmark Suite for Warehouse-Scale Computers. 325-327 - Yuxin Qin, Dejice Jacob, Jeremy Singer:
Characterizing Dynamic Memory Behavior in WebAssembly Workloads. 328-330 - Lishan Yang, George Papadimitriou, Dimitrios Sartzetakis, Adwait Jog, Evgenia Smirni, Dimitris Gizopoulos:
Probing Weaknesses in GPU Reliability Assessment: A Cross-Layer Approach. 331-333
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-27 21:34 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: