default search action
ISPD 2001: Sonoma County, CA, USA
- Sachin S. Sapatnekar, Manfred Wiesel:
Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001. ACM 2001, ISBN 1-58113-347-2 - Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh:
Differences in ASIC, COT and processor design (panel). 2 - Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. 4-9 - Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh:
An exact algorithm for coupling-free routing. 10-15 - Tao Lin, Lawrence T. Pileggi:
RC(L) interconnect sizing with second order considerations via posynomial programming. 16-21 - Yih-Chih Chou, Youn-Long Lin:
A performance-driven standard-cell placer based on a modified force-directed algorithm. 24-29 - Patrick H. Madden:
Reporting of standard cell placement results. 30-35 - Fook-Luen Heng, Lars Liebmann, Jennifer Lund:
Application of automated design migration to alternating phase shift mask design. 38-43 - Warren Grobman, Robert Boone, Cece Philbin, Bob Jarvis:
Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs. 45-51 - Franklin M. Schellenberg, Luigi Capodieci:
Impact of RET on physical layouts. 52-55 - Stephen P. Boyd, Lieven Vandenberghe, Abbas El Gamal, Sunghee Yun:
Design of robust global power and ground networks. 60-65 - Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation for power supply noise suppression. 66-71 - Andrew R. Conn, Chandramouli Visweswariah:
Overview of continuous optimization advances and applications to circuit tuning. 74-81 - Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
:
Design and analysis of physical design algorithms. 82-89 - Phillip J. Restle, Albert E. Ruehli, Steven G. Walker:
Multi-GHz interconnect effects in microprocessors. 93-97 - Wai-Kei Mak:
Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. 100-105 - Fei Li, Lei He:
Maximum current estimation considering power gating. 106-111 - Jinan Lou, Shankar Krishnamoorthy, Henry S. Sheng:
Estimating routing congestion using probabilistic analysis. 112-117 - Ruiqi Tian, Xiaoping Tang, D. F. Wong
Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. 118-123 - En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang:
Slicing floorplan design with boundary-constrained modules. 124-129 - Sabyasachi Das, Sunil P. Khatri:
A regularity-driven fast gridless detailed router for high frequency datapath designs. 130-135 - Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Revisiting floorplan representations. 138-143 - Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with super hierarchical constraints. 144-149 - Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
ECBL: an extended corner block list with solution space including optimum placement. 150-155 - Yingxin Pang, Chung-Kuan Cheng, Koen Lampaert, Weize Xie:
Rectilinear block packing using O-tree representation. 156-161 - Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh:
Congestion estimation during top-down placement. 164-169 - Yangdong Deng, Wojciech Maly:
Interconnect characteristics of 2.5-D system integration scheme. 171-175 - Wei-Jin Dai:
Hierarchical physical design methodology for multi-million gate chips. 179-181 - Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje:
Overcoming wireload model uncertainty during physical design. 182-189 - Zhaoyun Xing, Russell Kao:
A minimum cost path search algorithm through tile obstacles. 192-197 - Kolja Sulimma, Wolfgang Kunz:
An exact algorithm for solving difficult detailed routing problems. 198-203 - Ankireddy Nalamalpu, Wayne P. Burleson:
Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters. 204-211 - Rajeev Jayaraman:
Physical design for FPGAs. 214-221 - Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
A comparative study of two Boolean formulations of FPGA detailed routing constraints. 222-227 - Kaustav Banerjee, Massoud Pedram, Amir H. Ajami:
Analysis and optimization of thermal issues in high-performance VLSI. 230-237 - Ting-Yuan Wang, Charlie Chung-Ping Chen:
Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method. 238-243
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-26 00:59 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: