default search action
VLSI-SoC 2012: Santa Cruz, CA, USA - Selected Papers
- Andreas Burg, Ayse K. Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis:
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers. IFIP Advances in Information and Communication Technology 418, Springer 2013, ISBN 978-3-642-45072-3 - Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber:
FPGA-Based High-Speed Authenticated Encryption System. 1-20 - Qiuling Zhu, Larry T. Pileggi, Franz Franchetti:
A Smart Memory Accelerated Computed Tomography Parallel Backprojection. 21-44 - Andy Motten, Luc Claesen, Yun Pan:
Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure. 45-63 - Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic:
Spatially-Varying Image Warping: Evaluations and VLSI Implementations. 64-87 - Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson
, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. 88-106 - Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini
Configurable Low-Latency Interconnect for Multi-core Clusters. 107-124 - Zhibin Xiao, Bevan M. Baas:
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. 125-143 - Anelise Kologeski, Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro:
Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections. 144-161 - Davide Sabena, Luca Sterpone
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors. 162-180 - Seokjoong Kim, Matthew R. Guthaus:
SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture. 181-195 - Farhad Alibeygi Parsan, Scott C. Smith:
CMOS Implementation of Threshold Gates with Hysteresis. 196-216 - Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra
Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates. 217-233
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-26 00:58 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: