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International Journal of High Performance Systems Architecture, Volume 4
Volume 4, Number 1, 2012
- Yoonsuk Choi, Shahram Latifi:
Future prospects of DRAM: emerging alternatives. 1-12 - Mateus B. Rutzig
, Antonio Carlos Schneider Beck:
Mixing static and dynamic strategies for high performance and low area reconfigurable systems. 13-24 - Kanchan Manna, Santanu Chattopadhaya, Indranil Sengupta:
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison. 25-37 - Chifeng Wang, Nader Bagherzadeh
High-throughput differentiated service provision router architecture for wireless network-on-chip. 38-56 - Luneque Del Rio de Souza e Silva Junior
Static routing for applications mapped on NoC platform using ant colony algorithms. 57-64
Volume 4, Number 2, 2012
- Victor Wanderley Costa de Medeiros, Rodrigo Camarotti Ferreira da Rocha, Antonyus Pyetro do Amaral Ferreira
FPGA-based architecture to speed-up scientific computation in seismic applications. 65-77 - Pablo Igounet, Pablo Alfaro, Gabriel Usera
Towards a finite volume model on a many-core platform. 78-88 - Rafael Sachetto Oliveira
A parallel accelerated adaptive mesh algorithm for the solution of electrical models of the heart. 89-100 - Italo Epicoco
The performance model for a parallel SOR algorithm using the red-black scheme. 101-109 - Sparsh Mittal
A survey of architectural techniques for DRAM power management. 110-119
Volume 4, Number 3, 2013
- Daniel Honbo, Amit Pande, Alok N. Choudhary:
FPGA architecture for pairwise statistical significance estimation. 121-131 - Amir Gargouri, Mohamed Krid
Hardware implementation of new bell-shaped pulse mode neural network with on-chip learning and application to image processing. 132-143 - Paulo Renato de Souza Silva Sandres, Nadia Nedjah
Reconfigurable hardware for fuzzy controller. 144-166 - Yoonsuk Choi, Shahram Latifi:
Modern flash technologies: a flash translation layer perspective. 167-182
Volume 4, Number 4, 2013
- Aili Wang, Chao Wang, Xi Li, Xuehai Zhou, Nadia Nedjah
Services-oriented URL filtering and verification. 183-195 - Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh:
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. 196-203 - Joyashree Bag, Rashmi Ranjan Sahoo
Design and VLSI implementation of power efficient processor for object localisation in large WSN. 204-217 - Gayathri Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, Smruti R. Sarangi:
Amdahl's law in the era of process variation. 218-230 - Shima Mehrabi, Reza Faghih Mirzaee
Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors. 231-241
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