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Microprocessing and Microprogramming, Volume 34
Volume 34, Numbers 1-5, February 1992
- J. G. M. Kroon:
The software development environment at Rijkswaterstaat. 3-6 - Maciej Piechowka, Stanislaw Szejko:
An object-oriented kernel for distributed simulation of concurrent systems. 7-10 - Miroslav Svéda:
Microcontroller software engineering. 11-13 - Paola Nieddu:
A unifying approach to clientship, delegation and inheritance in object oriented languages. 15-18 - Mary Buchanan, Carol Britton:
Formal specification and object-oriented design. 19-22 - Massimo Annunziata, Sergio Calabrese, Raffaele Lorello:
SIPA: An activity-planning system. 23-26 - M. Pfeiffer, Rudolf Haggenmüller:
System engineering with DOMINO and GRAPES. 27-30 - Jan Janecek:
Pollux: A language for distributed system programming. 33-36 - Lecordier Richard, Martin Patrick:
Data flow processors for automated visual inspection. 37-40 - Yoo S. Kim, Song C. Moon:
Update synchronization pursuing site autonomy in heterogeneous distributed databases. 41-44 - Johan Ringström, Peter Fritzson, Johan Fagerström:
PREDULA a multi-paradigm parallel programming and debugging environment. 45-48 - Borut Jereb
, Ljubo Pipan:
Measuring parallelism in algorithms. 49-52 - Anton M. van Wezenbeek, Willem Jan Withagen:
Adaptive window working set replacement policies. 53-56 - Gerard J. M. Smit, Paul J. M. Havinga, Pierre G. Jansen:
On the design of a dynamic reconfigurable network switch. 59-62 - Yong I. Yoon, Song C. Moon:
Reliable transaction processing for real-time distributed database systems. 63-66 - Andrea Clematis
The conversation deadlock problem in client-server model. 67-71 - Peter Milligan, R. K. McConnell, S. A. Rea, Paul Sage:
Fortport: An environment for the development of parallel fortran programs. 73-74 - Peter Milligan, S. A. Rea, R. K. McConnell, H. R. J. Walters:
Parallel collocation modelling: A case study in developing efficient parallel codes. 77-80 - Harald-Reto Fonio, Adam Pawlak:
Rule-based synthesis using ADTs and term rewriting. 81-84 - J. Morán, S. Alexandres:
A comparison of some processor farm architectures. 85-88 - Jordi Carrabina
Digital neural network system based in new concepts on the recall phase dynamics. 89-92 - Daniel Mozos, Julio Septién, Francisco Tirado
Design control in a high level synthesis system. 93-96 - Vincenzo Piuri, Renato Stefanelli:
Fault-tolerant techniques for VLSI tree structures. 97-102 - P. Pramanik, Pradip K. Das, A. K. Bandyopadhyay, D. Q. M. Fay:
Avoidance of deadlock in loop structures - a two process solution. 103-106 - Petr Kroha, Peter Fritzson:
Software features of an extended single instruction machine. 109-112 - Xiaoming Fan:
Queue-based primitives for a multithreaded architecture. 113-116 - J. D. M. McKeever, D. R. W. Holton, R. M. McKeag:
Using transputers in a robot programming and control system. 117-120 - Nikola B. Serbedzija:
Parallel programming on a PC - a case study. 121-124 - Juan Manuel Adán Coello, Maurício Ferreira Magalhães:
Ster's multilevel programming model for distributed hard real-time systems. 125-128 - Alessandro Gandelli, Vincenzo Piuri:
A highly-parallel system for real-time electronic measurements. 129-132 - Gy. Ambrózy, István Cseke, Z. Fazekas, S. Zöld:
ARGUS - a PC based image processing workstation its software and some application examples. 135-138 - S. L. Horianopoulos, D. E. Metafas, Costas E. Goutis, Theodore L. Deliyannis:
A VLSI synthesis tool for complementary output delta modulation FIR filters. 139-142 - E. Randon, P. Sanchez, Eugenio Villar
ESP, a structure synthesis program. 143-145 - Marco Dorigo
Using transputers to increase speed and flexibility of genetics-based machine learning systems. 147-152 - Dimitrios Sampsonidis, M. Zamani:
An image analysis system for automatic measurements in solid state nuclear track detectors. 153-155 - Gabriel P. Silva, Júlio S. Aude:
Evaluation of a sparc architecture with harvard bus and branch target cache. 157-160 - Zdenek Blazek, Ivan Jelínek:
Multiprocessor monitoring system. 163-166 - Kiyeol Ryu, Seungryoul Maeng:
Specifying and inheriting concurrent objects. 167-170 - Peter Brezany, Viera Sipková:
Compiling a vector and array processing language for an associative processor. 171-174 - Handong Wu, Lars-Erik Thorelli, Abdel-Halim Smai:
Flow control support for efficient realization of the EDA model. 175-178 - Friedrich Mayer-Lindenberg:
Interactive software development for complex embedded systems. 179-182 - Jerzy J. Dabrowski:
Efficient timing verification via mixed-mode technique. 183-186 - Syhy-Chang Su, Prasenjit Biswas:
A memory-mapped interprocessor communication architecture using FIFO RAMs. 187-191 - Luis Gómez, Antonio Hernández, Antonio Núñez:
Timimg model for SDCFL digital circuits. 193-196 - Milan Ojstersek
Improving a time critical task execution time using an IPRESPS. 197-200 - Marek S. Tudruj
Multi-layer reconfigurable transputer systems with distributed control of link connections. 201-204 - Gy. Bango, Miklos Gardos, J. Miskolczi, I. Szabo, I. Renyi:
Design concepts and realization of the hardware structure of ARGUS image processing workstation. 207-210 - Nick Bailey, Alan Purvis, Peter D. Manning, Ian Bowler, Durham Music Technology:
Some observations on hierarchical, multiple-instruction-multiple-data computers. 211-214 - V. Polo, F. Fernández, A. Sánchez:
Parallel implementation of local averaging for image processing. 215-218 - J. Carazo, S. Alexandres, J. Morán:
Speech recognizer optimization and real-time implementation on a multitransputer array. 219-222 - Edil S. T. Fernandes, Claudson F. Bornstein, Cláudia M. D. Pereira:
Parallel code generation for super-scalar architectures. 223-226 - Fernando M. B. Barbosa, Edil S. T. Fernandes:
Dispatching simultaneous instructions. 227-230 - P. A. Kokkinidis, C. Metaxaki-Kossionidou:
An adaptive improvement of an image compression technique. 231-234 - Helnye Azaria, Yuval Elovici, Roger D. Hersch:
Multiple interfaces message passing system for transputer network. 237-242 - R. Mcconnell, J. Flanigan:
A simple switching system for transputer links. 243-246 - Francisco Javier López Aligué, M. Isabel Acevedo Sotoca, Miguel A. Jaramillo Morán:
Multimicrocomputer implementation of three-dimensional neural networks. 247-250 - Francisco J. Vico, Francisco Sandoval
Neural networks definition algorithm. 251-254
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