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Ciaran Toal
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2010 – 2019
- 2012
- [j2]Kieran McLaughlin, Dwayne Burns, Ciaran Toal, Colm McKillen, Sakir Sezer:
Fully hardware based WFQ architecture for high-speed QoS packet scheduling. Integr. 45(1): 99-109 (2012) - [c19]Ciaran Toal, Sakir Sezer, Dwayne Burns, Pei Xiao, Vincent F. Fusco:
A 1Gbps FPGA-based wireless baseband MIMO transceiver. SoCC 2012: 202-207 - 2010
- [c18]Pei Xiao, Ciaran Toal, Dwayne Burns, Vincent F. Fusco, Colin Cowan:
Transmit and receive filter design for OFDM based WLAN systems. WCSP 2010: 1-4
2000 – 2009
- 2009
- [j1]Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Xin Yang:
Design and Implementation of a Field Programmable CRC Circuit Architecture. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1142-1147 (2009) - 2007
- [c17]Ciaran Toal, Dwayne Burns, Kieran McLaughlin, Sakir Sezer, Stephen O'Kane:
An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing. AHS 2007: 613-618 - [c16]Motasem Abdelghani, Sakir Sezer, Emi Garcia, Jun Mu, Ciaran Toal:
FPGA-Based Lookup Circuit for Session-Based IP Packet Classification. AHS 2007: 619-624 - [c15]Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic:
An FPGA Based Memory Efficient Shared Buffer Implementation. FPL 2007: 661-664 - [c14]Ciaran Toal, Sakir Sezer, Xin Yang, Kieran McLaughlin, Dwayne Burns, Tiberiu Seceleanu:
Programmable CRC circuit architecture. SoCC 2007: 123-126 - 2006
- [b1]Ciaran Toal:
Exploration of high performance frame processing architectures. Queen's University Belfast, UK, 2006 - [c13]Ciaran Toal, Sakir Sezer:
Investigation into programmability for layer 2 protocol frame delineation architectures. IPDPS 2006 - [c12]Ciaran Toal, Sakir Sezer, Xin Yang:
A VLSI GFP Frame Delineation Circuit. ISVLSI 2006: 454-455 - 2005
- [c11]Ciaran Toal, Sakir Sezer:
A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA. AICT/SAPIR/ELETE 2005: 357-362 - [c10]Stephen O'Kane, Sakir Sezer, Ciaran Toal:
Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch. SoCC 2005: 283-286 - 2004
- [c9]Sakir Sezer, Emi Garcia-Palacios, Ciaran Toal, Stephen Dawson:
Architecture and implementation of a novel tag computation circuit for broadband wireless access packet scheduling. ICC 2004: 3979-3983 - [c8]Emi Garcia-Palacios, Sakir Sezer, Ciaran Toal, Stephen Dawson:
Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access. ICT 2004: 876-884 - [c7]Ciaran Toal, Sakir Sezer:
The Implementation of Scalable ATM Frame Delineation Circuits. ICT 2004: 1047-1056 - [c6]Sakir Sezer, Ciaran Toal, Emi Garcia, Victoria Stewart:
A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling. IPDPS 2004 - [c5]Ciaran Toal, Sakir Sezer:
Exploration of GFP frame delineation architectures for network processing. SoCC 2004: 159-162 - 2003
- [c4]Ciaran Toal, Sakir Sezer, Xing Yu:
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. FCCM 2003: 271-272 - [c3]Brendan McAllister, Sakir Sezer, Ciaran Toal:
Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. FPL 2003: 1149-1152 - [c2]Ciaran Toal, Sakir Sezer:
A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET. IPDPS 2003: 179 - [c1]Ciaran Toal, Sakir Sezer:
A 32-Bit SoPC Implementation of a P5. ISCC 2003: 504-507
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