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Prabir Saha
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2020 – today
- 2024
- [j10]Srikant Kumar Beura, Bishnulatpam Pushpa Devi, Prabir Saha
, Pramod Kumar Meher:
Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers. Circuits Syst. Signal Process. 43(6): 3748-3774 (2024) - [j9]Srikant Kumar Beura, Sudeshna Manjari Mahanta, Bishnulatpam Pushpa Devi
Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication. Integr. 94: 102096 (2024) - 2022
- [j8]Sheba Diamond Thabah, Prabir Saha
Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier. J. Circuits Syst. Comput. 31(4): 2250062:1-2250062:23 (2022) - 2021
- [j7]Sheba Diamond Thabah, Prabir Saha
Improved Signed Binary Multiplier Through New Partial Product Generation Scheme. J. Circuits Syst. Comput. 30(9): 2150162:1-2150162:21 (2021) - [c7]Srikant Kumar Beura
Design and Analysis of Inexact 3: 2 Compressor-based Radix-4 Multiplier towards Image Multiplication. ICCCNT 2021: 1-6 - 2020
- [j6]Rekib Uddin Ahmed
Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation. Period. Polytech. Electr. Eng. Comput. Sci. 64: 106-114 (2020) - [j5]Sheba Diamond Thabah, Prabir Saha
A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder. Period. Polytech. Electr. Eng. Comput. Sci. 64(4): 343-351 (2020) - [j4]Sheba Diamond Thabah, Prabir Saha
New design approaches of reversible BCD encoder using Peres and Feynman gates. ICT Express 6(1): 38-42 (2020)
2010 – 2019
- 2017
- [c6]Rekib Uddin Ahmed
Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime. iNIS 2017: 179-183 - 2015
- [c5]Prabir Saha
Implementation of high speed processor for computing convolution sum for DSP applications. IMCOM 2015: 51:1-51:6 - [c4]Deepak Kumar
Integer division technique for signal processing applications. IMCOM 2015: 52:1-52:4 - 2014
- [j3]Prabir Saha
Improved matrix multiplier design for high-speed digital signal processing applications. IET Circuits Devices Syst. 8(1): 27-37 (2014) - [j2]Prabir Saha
Design of 64-Bit Squarer Based on Vedic Mathematics. J. Circuits Syst. Comput. 23(7) (2014) - 2013
- [c3]Prabir Saha
Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications. ISED 2013: 41-45 - 2012
- [c2]Prabir Saha
Design of High Speed Vedic Multiplier for Decimal Number System. VDAT 2012: 79-88 - 2011
- [j1]Prabir Saha
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. Microelectron. J. 42(12): 1343-1352 (2011) - [c1]Prabir Saha
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. ISED 2011: 67-71
Coauthor Index
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