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Kevin Zhang 0001
Person information
- affiliation: Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan
- affiliation (until 2016): Intel Corporation, Hillsboro, OR, USA
- affiliation (PhD 1994): Duke University, Durham, NC, USA
Other persons with the same name
- Kevin Zhang — disambiguation page
- Kevin Zhang 0002
— Carnegie Mellon University, Robotics Institute, Pittsburgh, PA, USA
- Kevin Zhang 0003
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2020 – today
- 2024
- [c25]Kevin Zhang:
1.1 Semiconductor Industry: Present & Future. ISSCC 2024: 10-15 - 2021
- [c24]Kevin Zhang, Makoto Ikeda:
Session 1 Overview Plenary Session - Invited Papers. ISSCC 2021: 7-8
2010 – 2019
- 2018
- [c23]Kevin Zhang:
Circuit Design in Nano-Scale CMOS Technologies. A-SSCC 2018: 1-4 - [c22]Kevin Zhang:
Circuit design in nano-scale CMOS technologies. VLSI-DAT 2018: 1 - 2017
- [j17]Jaydeep P. Kulkarni
5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. IEEE J. Solid State Circuits 52(1): 229-239 (2017) - 2016
- [j16]Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang:
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. IEEE J. Solid State Circuits 51(1): 222-229 (2016) - [j15]Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang:
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 51(4): 1003-1008 (2016) - [c21]Kevin Zhang:
Circuit Design in Nano-Scale CMOS Technologies. ISPD 2016: 1 - [c20]Kevin Zhang:
Foreword: Silicon systems for the Internet of Everything. ISSCC 2016: 5 - [c19]Anantha P. Chandrakasan, Kevin Zhang:
Session 1 overview: Plenary session. ISSCC 2016: 6-7 - [c18]John Keane, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. ISSCC 2016: 308-309 - [c17]Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang:
A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. VLSI Circuits 2016: 1-2 - 2015
- [j14]Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima
A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. IEEE J. Solid State Circuits 50(1): 150-157 (2015) - [c16]Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang:
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. ISSCC 2015: 1-3 - [c15]Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang:
Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process. VLSIC 2015: 174- - [c14]Kyung-Hoae Koo, Liqiong Wei, John Keane, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang:
A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. VLSIC 2015: 266- - 2014
- [c13]Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. ISSCC 2014: 230-231 - [c12]Mesut Meterelliyoz, Fuad H. Al-amoody, Umut Arslan, Fatih Hamzaoglu, Luke Hood, Manoj B. Lal, Jeffrey L. Miller, Anand Ramasundar, Dan Soltman, Ifar Wan, Yih Wang
2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology. VLSIC 2014: 1-2 - 2013
- [j13]Eric Karl, Yih Wang
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. IEEE J. Solid State Circuits 48(1): 150-158 (2013) - 2012
- [c11]Kevin Zhang:
Challenges and opportunities for circuit design in nano-scale CMOS technologies. ESSCIRC 2012: 28-29 - [c10]Eric Karl, Yih Wang
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. ISSCC 2012: 230-232 - 2011
- [j12]Fatih Hamzaoglu, Yih Wang
Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. IEEE Des. Test Comput. 28(1): 22-31 (2011) - [j11]Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. IEEE J. Solid State Circuits 46(1): 76-84 (2011) - 2010
- [j10]Yih Wang
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. IEEE J. Solid State Circuits 45(1): 103-110 (2010) - [j9]Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. IEEE J. Solid State Circuits 45(4): 751-758 (2010) - [j8]Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang:
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS. IEEE J. Solid State Circuits 45(4): 863-868 (2010) - [c9]Hyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang
A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. ISSCC 2010: 346-347
2000 – 2009
- 2009
- [j7]Fatih Hamzaoglu, Kevin Zhang, Yih Wang
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. IEEE J. Solid State Circuits 44(1): 148-154 (2009) - [j6]Muhammad M. Khellah
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE J. Solid State Circuits 44(4): 1199-1208 (2009) - [c8]Kevin Zhang:
Circuit design in nano-scale CMOS era: opportunities & challenges. ISLPED 2009: 157-158 - [c7]Yih Wang
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. ISSCC 2009: 456-457 - 2008
- [j5]Yih Wang
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. IEEE J. Solid State Circuits 43(1): 172-179 (2008) - [c6]Fatih Hamzaoglu, Kevin Zhang, Yih Wang
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. ISSCC 2008: 376-377 - [c5]Kevin Zhang:
Embedded Memory Design for Nano-Scale VLSI Systems (Forum). ISSCC 2008: 650-651 - 2007
- [j4]Muhammad M. Khellah
A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42(1): 233-242 (2007) - [c4]Kevin Zhang, Hiroyuki Yamauchi
SRAM. ISSCC 2007: 320-321 - [c3]Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr:
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. ISSCC 2007: 324-606 - 2006
- [j3]Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. IEEE J. Solid State Circuits 41(1): 146-151 (2006) - [c2]Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. ISSCC 2006: 2572-2581 - 2005
- [j2]Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. IEEE J. Solid State Circuits 40(4): 895-901 (2005) - [c1]Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De:
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ISLPED 2005: 26-29 - 2002
- [j1]Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 91-95 (2002)
Coauthor Index
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