Corrigendum to "High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability". - Chu, Ting-Li; Yu, Sin-Hong; Hwang, Chorng-Sii (VLSI Design, 2017)

All-digital deskew buffer using a hybrid control scheme. - Chu, Ting-Li; Chu, Wen-Yu; Fujii, Yasuyoshi; Hwang, Chorng-Sii (2015)

A clock generator based on multiplying delay-locked loop. - Hwang, Chorng-Sii; Chu, Ting-Li; Chen, Wen-Cheng (2014)

High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability. - Chu, Ting-Li; Yu, Sin-Hong; Hwang, Chorng-Sii (VLSI Design, 2013)

DLL-based programmable clock multiplier using differential toggle-pulsed latch. - Hwang, Chorng-Sii; Chu, Ting-Li; Chen, Po-Hsun (2013)

High-accuracy programmable timing generator with wide-range tuning capability. - Chu, Ting-Li; Yu, Sin-Hong; Hwang, Chorng-Sii (2012)