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Ho-Cheung Ng
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2020 – today
- 2024
- [j5]Junyi Liu
, Aleksandar Dragojevic, Shane T. Fleming, Antonios Katsarakis, Dario Korolija, Igor Zablotchi, Ho-Cheung Ng
Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC. IEEE Trans. Computers 73(3): 857-871 (2024) - 2023
- [i6]Junyi Liu, Aleksandar Dragojevic, Shane Flemming, Antonios Katsarakis, Dario Korolija, Igor Zablotchi, Ho-Cheung Ng, Anuj Kalia, Miguel Castro:
Honeycomb: ordered key-value store acceleration on an FPGA-based SmartNIC. CoRR abs/2303.14259 (2023) - 2022
- [j4]Maolin Wang
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. 33(7): 2853-2866 (2022) - 2021
- [c18]Ho-Cheung Ng, Izaak Coleman
Reconfigurable Acceleration of Short Read Mapping with Biological Consideration. FPGA 2021: 229-239 - 2020
- [j3]Izaak Coleman
GeDi: applying suffix arrays to increase the repertoire of detectable SNVs in tumour genomes. BMC Bioinform. 21(1): 45 (2020) - [c17]Ho-Cheung Ng, Shuanglong Liu, Izaak Coleman
Acceleration of Short Read Alignment with Runtime Reconfiguration. FPT 2020: 256-262
2010 – 2019
- 2019
- [j2]Erwei Wang
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52(2): 40:1-40:39 (2019) - [c16]Jiuxi Meng, Nadeen Gebara, Ho-Cheung Ng, Paolo Costa, Wayne Luk:
Investigating the Feasibility of FPGA-based Network Switches. ASAP 2019: 218-226 - [c15]Ringo S. W. Chu, Ho-Cheung Ng, Xiwei Wang, Wayne Luk:
Convolution Based Spectral Partitioning Architecture for Hyperspectral Image Classification. IGARSS 2019: 3962-3965 - [i5]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR abs/1901.06955 (2019) - [i4]Ringo S. W. Chu, Ho-Cheung Ng, Xiwei Wang, Wayne Luk:
Convolution Based Spectral Partitioning Architecture for Hyperspectral Image Classification. CoRR abs/1906.11981 (2019) - 2018
- [j1]Shuanglong Liu
Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA. ACM Trans. Reconfigurable Technol. Syst. 11(3): 19:1-19:22 (2018) - [c14]Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Hardware Compilation of Deep Neural Networks: An Overview. ASAP 2018: 1-8 - [c13]Ho-Cheung Ng, Shuanglong Liu, Wayne Luk:
ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development. FPGA 2018: 189-198 - [c12]Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu:
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. FPL 2018: 147-154 - [c11]Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation. FPL 2018: 287-294 - [c10]Hongxiang Fan, Shuanglong Liu, Martin Ferianc
A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA. FPT 2018: 14-21 - [c9]Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. FPT 2018: 30-37 - [i3]Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu:
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. CoRR abs/1809.03318 (2018) - 2017
- [c8]Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So
A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. FCCM 2017: 84 - [c7]Ho-Cheung Ng, Shuanglong Liu, Wayne Luk:
Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts. FPL 2017: 1-8 - 2016
- [c6]Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT 2016: 261-264 - [c5]Sam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So
Towards FPGA-assisted spark: An SVM training acceleration case study. ReConFig 2016: 1-6 - [c4]Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig 2016: 1-6 - [i2]Ho-Cheung Ng, Cheng Liu, Hayden Kwok-Hay So:
A Soft Processor Overlay with Tightly-coupled FPGA Accelerator. CoRR abs/1606.06483 (2016) - 2015
- [b1]Ho-Cheung Ng:
A soft processor overlay with tightly-coupled FPGA accelerator. University of Hong Kong, Pokfulam, Hong Kong, 2015 - [c3]Cheng Liu
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. FPT 2015: 56-63 - [i1]Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So:
Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. CoRR abs/1509.00042 (2015) - 2014
- [c2]Jun-qi Deng, Francis Chi-Moon Lau, Ho-Cheung Ng, Yu-Kwong Kwok, Hung-Kwan Chen, Yuheng Liu:
WIJAM: A Mobile Collaborative Improvisation Platform under Master-players Paradigm. NIME 2014: 407-410 - 2013
- [c1]Ho-Cheung Ng, Yuk-Ming Choi, Hayden Kwok-Hay So
Direct virtual memory access from FPGA for high-productivity heterogeneous computing. FPT 2013: 458-461
Coauthor Index
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