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Yi-Wei Chiu
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2020 – today
- 2023
- [c8]Yen-Wen Chen, Yi-Wei Chiu, Yu-Sin Liu, Chih-Yu Huang, Yu-Chun Shen:
AI Powered Multi-model Content Creation For Virtual Gallery Using Learning Machine. UEMCON 2023: 704-709
2010 – 2019
- 2016
- [c7]Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang:
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. ISCAS 2016: 1014-1017 - 2015
- [c6]Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee:
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. ISCAS 2015: 2549-2552 - 2014
- [j1]Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang:
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2578-2585 (2014) - [c5]Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee:
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. SoCC 2014: 160-164 - 2013
- [c4]Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang:
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. ISLPED 2013: 51-56 - 2012
- [c3]Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu:
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS 2012: 116-119 - 2011
- [c2]Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang:
8T single-ended sub-threshold SRAM with cross-point data-aware write operation. ISLPED 2011: 169-174
2000 – 2009
- 2008
- [c1]Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee:
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. ISCAS 2008: 3426-3429
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