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Jun Shiomi
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2020 – today
- 2024
- [j21]Dehua Liang
, Jun Shiomi
StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. IEEE Open J. Circuits Syst. 5: 211-223 (2024) - [j20]Dehua Liang
A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits. ACM Trans. Embed. Comput. Syst. 23(6): 91:1-91:20 (2024) - [c29]Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi:
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. ASPDAC 2024: 618-624 - [c28]Itsuki Takada, Daiki Nitto, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi, Ryoichi Shinkuma:
Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring. CCNC 2024: 400-405 - 2023
- [j19]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 542-550 (2023) - [j18]Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi:
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. IEICE Trans. Electron. 106(10): 546-555 (2023) - [c27]Dehua Liang
DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. ASP-DAC 2023: 416-422 - [c26]Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata:
A Triturated Sensing System. ISSCC 2023: 216-217 - [c25]Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura:
A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. ISSCC 2023: 218-219 - 2022
- [j17]Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara:
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 518-529 (2022) - [j16]Dehua Liang
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. 105-D(7): 1273-1282 (2022) - [c24]Dehua Liang
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. ASP-DAC 2022: 43-49 - [c23]Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi:
Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. COOL CHIPS 2022: 1-6 - [c22]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region. LASCAS 2022: 1-4 - [c21]Kuon Akiyama, Ryoichi Shinkuma, Jun Shiomi:
Real-time adaptive data filtering with multiple sensors for indoor monitoring. NOMS 2022: 1-3 - [c20]Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera:
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC 2022: 1-6 - 2021
- [j15]Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1477-1487 (2021) - [j14]Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1488-1498 (2021) - [j13]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1546-1554 (2021) - [j12]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1566-1576 (2021) - [j11]Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera:
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation. IEICE Trans. Electron. 104-C(10): 617-624 (2021) - [j10]Hongjie Xu
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching. IEEE Open J. Circuits Syst. 2: 144-155 (2021) - [c19]Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. DAC 2021: 139-144 - [c18]Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara:
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED 2021: 300-306 - 2020
- [c17]Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera:
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias. APCCAS 2020: 31-34 - [c16]Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation. ACM Great Lakes Symposium on VLSI 2020: 21-26 - [c15]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. ICRC 2020: 95-101 - [c14]Khyati Kiyawat
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI 2020: 415-421 - [c13]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. ISVLSI 2020: 488-493 - [c12]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region. SoCC 2020: 236-241
2010 – 2019
- 2019
- [j9]Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A Design Method of a Cell-Based Amplifier for Body Bias Generation. IEICE Trans. Electron. 102-C(7): 565-572 (2019) - [j8]Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1741-1750 (2019) - [j7]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1751-1759 (2019) - [j6]Jun Shiomi, Tohru Ishihara
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. Integr. 65: 201-210 (2019) - [c11]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. ASP-DAC 2019: 203-209 - [c10]Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi:
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC 2019: 15-21 - 2018
- [j5]Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
Minimum Energy Point Tracking with All-Digital On-Chip Sensors. J. Low Power Electron. 14(2): 227-235 (2018) - [c9]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. ICRC 2018: 1-6 - [c8]Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. PATMOS 2018: 237-242 - 2017
- [b1]Jun Shiomi:
Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits. Kyoto University, Japan, 2017 - [j4]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2764-2775 (2017) - [c7]Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera:
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC 2017: 56-61 - 2016
- [j3]Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2463-2472 (2016) - [c6]Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. ASP-DAC 2016: 691-696 - [c5]Jun Shiomi, Tohru Ishihara
Variability- and correlation-aware logical effort for near-threshold circuit design. ISQED 2016: 18-23 - [c4]Jun Shiomi, Tohru Ishihara
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. PATMOS 2016: 44-49 - 2015
- [j2]Jun Shiomi, Tohru Ishihara
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1455-1466 (2015) - [j1]Islam A. K. M. Mahfuzul
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. IEEE J. Solid State Circuits 50(11): 2475-2490 (2015) - [c3]Jun Shiomi, Tohru Ishihara
Microarchitectural-level statistical timing models for near-threshold circuit design. ASP-DAC 2015: 87-93 - [c2]Jun Shiomi, Tohru Ishihara
An energy-efficient on-chip memory structure for variability-aware near-threshold operation. ISQED 2015: 23-28 - 2014
- [c1]Islam A. K. M. Mahfuzul
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. A-SSCC 2014: 45-48
Coauthor Index
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