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Tsuneo Nakata
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2020 – today
- 2021
- [c14]Takeo Ohseki, Kosuke Yamazaki, Daiki Maemoto, Shigeki Kawai, Tsuneo Nakata, Akira Itou:
Data Traffic Offloading and Rate Control for Vehicles Using Radio Environment, Network Load and Route Planning. PIMRC 2021: 1463-1468
2010 – 2019
- 2016
- [j2]Yuji Kamiya, Toru Nagura, Shigeki Kawai, Tsuneo Nakata:
Precise Location by Fingerprinting Road Segments with Variation of Broadcast Wave Reception. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1465-1472 (2016) - 2014
- [c13]Tsuneo Nakata, Shigeki Kawai:
Precise Location by Fingerprinting Road Segments with Variation of Wireless Reception. VTC Spring 2014: 1-5
2000 – 2009
- 2005
- [c12]Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata:
Integrating UML into SoC Design Process. DATE 2005: 836-837 - 2004
- [c11]Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata:
System-on-chip validation using UML and CWL. CODES+ISSS 2004: 92-97 - [c10]Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro Kuroki, Yoichi Endo, Takashi Hasegawa:
System-on-Chip Verification Process Using UML. UML Satellite Activities 2004: 138-149 - 2003
- [j1]Tsuneo Nakata:
Multi-event algorithms and protocols for fast and robust distributed mesh provisioning and restoration. Bell Labs Tech. J. 7(3): 23-39 (2003) - 2002
- [c9]Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu:
An Object-Oriented Design Process for System-on-Chip Using UML. ISSS 2002: 249-254 - [c8]Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 11-13 - 2001
- [c7]Kwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata:
A Method of Static Compaction of Test Stimuli. Asian Test Symposium 2001: 137-144 - 2000
- [c6]Subir K. Roy
, Hiroaki Iwashita, Tsuneo Nakata:
Formal verification based on assume and guarantee approach - a case study (short paper). ASP-DAC 2000: 77-80 - [c5]Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata:
Dataflow Analysis for Resource Contention and Register Leakage Properties. VLSI Design 2000: 418-423
1990 – 1999
- 1998
- [c4]Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose:
An approach to verify a large scale system-on-a-chip using symbolic model checking. ICCD 1998: 308-313 - 1997
- [c3]Hiroaki Iwashita, Tsuneo Nakata:
Forward model checking techniques oriented to buggy designs. ICCAD 1997: 400-404 - 1996
- [c2]Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose:
CTL model checking based on forward state traversal. ICCAD 1996: 82-87 - 1994
- [c1]Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose:
Automatic test program generation for pipelined processors. ICCAD 1994: 580-583
Coauthor Index
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