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Jef L. van Meerbergen
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2010 – 2019
- 2011
- [c60]Michiel Rooijakkers, Chiara Rabotti, Martijn Bennebroek, Jef L. van Meerbergen, Massimo Mischi:
Low-complexity R-peak detection in ECG signals: A preliminary step towards ambulatory fetal monitoring. EMBC 2011: 1761-1764 - [c59]Frank Bouwens, Jos Huisken
, Harmke de Groot, Martijn Bennebroek, Anteneh A. Abbo, Octavio Santana, Jef L. van Meerbergen, Antoine Fraboulet:
A dual-core system solution for wearable health monitors. ACM Great Lakes Symposium on VLSI 2011: 379-382
2000 – 2009
- 2009
- [j22]Andreas Hansson, Benny Akesson, Jef L. van Meerbergen:
Multi-processor programming in the embedded system curriculum. SIGBED Rev. 6(1): 9 (2009) - [j21]Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen:
Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. J. Signal Process. Syst. 57(1): 107-119 (2009) - 2008
- [j20]Aleksandar Beric, Jef L. van Meerbergen, Gerard de Haan, Ramanathan Sethuraman:
Memory-Centric Video Processing. IEEE Trans. Circuits Syst. Video Technol. 18(4): 439-452 (2008) - [c58]Arno Moonen, Marco Bekooij, René van den Berg, Jef L. van Meerbergen:
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip. DATE 2008: 300-305 - [c57]Jochem Govers, Jos Huisken
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. HiPEAC 2008: 82-96 - 2007
- [c56]Arno Moonen, Marco Bekooij, René van den Berg, Jef L. van Meerbergen:
Decoupling of Computation and Communication with a Communication Assist. DSD 2007: 63-68 - [c55]Peter Poplavko, Twan Basten
Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism. DSD 2007: 228-235 - [c54]Michael De Nil, Lennart Yseboodt, Frank Bouwens, Jos Hulzink, Mladen Berekovic, Jos Huisken, Jef L. van Meerbergen:
Ultra Low Power ASIP Design for Wireless Sensor Nodes. ICECS 2007: 1352-1355 - [c53]Arno Moonen, Marco Bekooij, René van den Berg, Jef L. van Meerbergen:
Practical and Accurate Throughput Analysis with the Cyclo Static Dataflow Model. MASCOTS 2007: 238-245 - [c52]Milan Pastrnak, Peter H. N. de With, Jef L. van Meerbergen:
Real-time aware rendering of scalable arbitrary-shaped MPEG-4 decoder for multiprocessor systems. Real-Time Image Processing 2007: 64960D - [c51]Lennart Yseboodt, Michael De Nil, Jos Huisken
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. SAMOS 2007: 385-395 - [c50]Marco Bekooij, Maarten Wiggers, Jef L. van Meerbergen:
Efficient buffer capacity and scheduler setting computation for soft real-time stream processing applications. SCOPES 2007: 1-10 - 2006
- [j19]Milan Pastrnak, Peter H. N. de With, Jef L. van Meerbergen:
Qos concept for scalable MPEG-4 video object decoding on multimedia (NoC) chips. IEEE Trans. Consumer Electron. 52(4): 1418-1426 (2006) - [c49]Akash Kumar
Global Analysis of Resource Arbitration for MPSoC. DSD 2006: 71-78 - [c48]Milan Pastrnak, Peter H. N. de With, Jef L. van Meerbergen:
Realization of QoS management using negotiation algorithms for multiprocessor NoC. ISCAS 2006 - [c47]Chris Bartels, Jos Huisken
Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip. VLSI-SoC 2006: 80-85 - [c46]Arno Moonen, Chris Bartels, Marco Bekooij, René van den Berg, Harpreet Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huisken
Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies. VLSI-SoC (Selected Papers) 2006: 317-336 - 2005
- [j18]Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan:
Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. IEEE Trans. Circuits Syst. Video Technol. 15(4): 508-527 (2005) - [j17]Calin Ciordas, Twan Basten
An event-based monitoring service for networks on chip. ACM Trans. Design Autom. Electr. Syst. 10(4): 702-723 (2005) - [j16]Aleksandar Beric, Gerard de Haan, Ramanathan Sethuraman, Jef L. van Meerbergen:
An Efficient Picture-Rate Up-Converter. J. VLSI Signal Process. 41(1): 49-63 (2005) - [c45]Aleksandar Beric, Gerard de Haan, Jef L. van Meerbergen, Ramanathan Sethuraman:
Algorithm/architecture co-design of the generalized sampling theorem based de-interlacer [video signal processing]. ISCAS (3) 2005: 2943-2946 - [c44]Peter Poplavko, Twan Basten
Extended abstract: estimation times of on-chip multiprocessor stream-oriented applications. MEMOCODE 2005: 250-251 - [c43]Orlando Moreira, Jan David Mol, Marco Bekooij, Jef L. van Meerbergen:
Multiprocessor Resource Allocation for Hard-Real-Time Streaming with a Dynamic Job-Mix. IEEE Real-Time and Embedded Technology and Applications Symposium 2005: 332-341 - [c42]Marco Bekooij, Jef L. van Meerbergen, Sonali Parma:
Performance Guarantees by Simulation of Process Networks. SCOPES 2005: 10-19 - [c41]Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan:
Memory-Centric Motion Estimator. VLSI Design 2005: 816-819 - 2004
- [c40]Marc Quax, Jos Huisken
A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver. DATE 2004: 230-235 - [c39]Calin Ciordas, Twan Basten
An event-based network-on-chip monitoring service. HLDVT 2004: 149-154 - [c38]Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Gerard Veldman, Jef L. van Meerbergen, Gerard de Haan:
Streaming scratchpad memory organization for video applications. Circuits, Signals, and Systems 2004: 427-432 - [c37]Marco Bekooij, Orlando Moreira, Peter Poplavko, Bart Mesman, Milan Pastrnak, Jef L. van Meerbergen:
Predictable Embedded Multiprocessor System Design. SCOPES 2004: 77-91 - [c36]Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto:
A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter. VLSI Design 2004: 1083- - 2003
- [c35]Peter Poplavko, Twan Basten, Marco Bekooij, Jef L. van Meerbergen, Bart Mesman:
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. CASES 2003: 63-72 - [c34]Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, Erwin Waterlander:
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. DATE 2003: 10350-10355 - [c33]Katarzyna Leijten-Nowak, Jef L. van Meerbergen:
An FPGA architecture with enhanced datapath functionality. FPGA 2003: 195-204 - [c32]Aleksandar Beric, Gerard de Haan, Jef L. van Meerbergen, Ramanathan Sethuraman:
Towards an efficient high quality picture-rate up-converter. ICIP (2) 2003: 363-366 - [p1]Kees Goossens, John Dielissen, Jef L. van Meerbergen, Peter Poplavko, Andrei Radulescu, Edwin Rijpkema, Erwin Waterlander, Paul Wielage:
Guaranteeing the Quality of Services in Networks on Chip. Networks on Chip 2003: 61-82 - 2002
- [c31]Kees Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen:
Networks on Silicon: Combining Best-Effort and Guaranteed Services. DATE 2002: 423-425 - [c30]Katarzyna Leijten-Nowak, Jef L. van Meerbergen:
Embedded Reconfigurable Logic Core for DSP Applications. FPL 2002: 89-101 - 2001
- [c29]John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken
Power-efficient layered turbo decoder processor. DATE 2001: 246-251 - [c28]Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen:
Phase coupled operation assignment for VLIW processors with distributed register files. ISSS 2001: 118-123 - [c27]Sias Mostert, Nathalie Cossement, Rudy Lauwereins, Jef L. van Meerbergen:
DF*: Modeling Dynamic Process Creation and Events for Interactive Multimedia Applications. IEEE International Workshop on Rapid System Prototyping 2001: 122-127 - 2000
- [j15]Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
Prophid: A Platform-Based Design Method. Des. Autom. Embed. Syst. 6(1): 5-37 (2000) - [j14]Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Gert-Jan van Rootselaar:
Heterogeneous multiprocessor for the management of real-time video and graphics streams. IEEE J. Solid State Circuits 35(11): 1722-1731 (2000) - [j13]Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess:
Constraint analysis for code generation: basic techniques and applications in FACTS. ACM Trans. Design Autom. Electr. Syst. 5(4): 774-793 (2000) - [c26]Françoise Harmsze, Adwin H. Timmer, Jef L. van Meerbergen:
Memory Arbitration and Cache Management in Stream-Based Systems. DATE 2000: 257-262 - [c25]Bernardo Kastrup
Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. FPL 2000: 695-706
1990 – 1999
- 1999
- [j12]Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
Constraint analysis for DSP code generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(1): 44-57 (1999) - [j11]Peter H. N. de With, Egbert G. T. Jaspers, Jef L. van Meerbergen, Adwin H. Timmer, Marino T. J. Strik:
A video display processing platform for future TV concepts. IEEE Trans. Consumer Electron. 45(4): 1230-1240 (1999) - [c24]Bernardo Kastrup
Seeking (the right) Problems for the Solutions of Reconfigurable Computing. FPL 1999: 520-525 - 1998
- [j10]Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen, Albert van der Werf:
The Complexity of Multidimensional Periodic Scheduling. Discret. Appl. Math. 89(1-3): 213-242 (1998) - [c23]Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. DATE 1998: 125-131 - [c22]Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
A Constraint Driven Approach to Loop Pipelining and Register Binding. DATE 1998: 377-383 - 1997
- [c21]Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen:
Multidimensional periodic scheduling: a solution approach. ED&TC 1997: 468-474 - [c20]Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
PROPHID: a data-driven multi-processor architecture for high-performance DSP. ED&TC 1997: 611 - [c19]Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. ICCD 1997: 164-169 - [c18]Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
Constraint Analysis for DSP Code Generation. ISSS 1997: 33-40 - 1996
- [c17]Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen, Albert van der Werf:
Multidimensional Periodic Scheduling Model and Complexity. Euro-Par, Vol. II 1996: 226-235 - 1995
- [j9]Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Jef L. van Meerbergen, Albert van der Werf:
Improved force-directed scheduling in high-throughput digital signal processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 945-960 (1995) - [j8]Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh, Albert van der Werf:
PHIDEO: High-level synthesis for high throughput applications. J. VLSI Signal Process. 9(1-2): 89-104 (1995) - [c16]Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess:
Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. DAC 1995: 593-598 - [c15]Marino T. J. Strik, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess, Stefaan Note:
Efficient code generation for in-house DSP-cores. ED&TC 1995: 244-251 - [c14]Jeroen A. J. Leijten, Jef L. van Meerbergen, Jochen A. G. Jess:
Analysis and reduction of glitches in synchronous networks. ED&TC 1995: 398-403 - 1994
- [c13]Douglas M. Grant, Jef L. van Meerbergen, Paul E. R. Lippens:
Optimization of Address Generator Hardware. EDAC-ETC-EUROASIC 1994: 325-329 - [c12]Albert van der Werf, Jef L. van Meerbergen, Emile H. L. Aarts, Wim F. J. Verhaegh, Paul E. R. Lippens:
Efficient timing constraint derivation for optimal retiming high speed processing units. HLSS 1994: 48-53 - 1993
- [j7]Jef L. van Meerbergen, Paul E. R. Lippens, B. T. McSweeney, Wim F. J. Verhaegh, Albert van der Werf, A. van Zanten:
Architectural strategies for high-throughput applications. J. VLSI Signal Process. 5(2-3): 201-220 (1993) - [j6]Jos Huisken
Synthesis of synchronous communication hardware in a multiprocessor architecture. J. VLSI Signal Process. 6(3): 289-299 (1993) - [c11]Paul E. R. Lippens, Jef L. van Meerbergen, Wim F. J. Verhaegh, Albert van der Werf:
Allocation of multiport memories for hierarchical data stream. ICCAD 1993: 728-735 - [c10]Albert van der Werf, Emile H. L. Aarts, E. W. Heijnen, Jef L. van Meerbergen, Wim F. J. Verhaegh, Paul E. R. Lippens:
A new method for retiming multi-functional processing units. VLSI 1993: 191-200 - 1992
- [j5]Rob Woudsma, Jef L. van Meerbergen:
Consumer applications: a driving force for high-level synthesis of signal-processing architectures. IEEE Micro 12(4): 20-33 (1992) - [c9]Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Albert van der Werf, Jef L. van Meerbergen:
Efficiency improvements for force-directed scheduling. ICCAD 1992: 286-291 - [c8]Albert van der Werf, M. J. H. Peek, Emile H. L. Aarts, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh:
Area optimization of multi-functional processing units. ICCAD 1992: 292-299 - 1991
- [c7]Paul E. R. Lippens, Jef L. van Meerbergen, Albert van der Werf, Wim F. J. Verhaegh, B. T. McSweeney, Jos Huisken, O. McArdle:
PHIDEO: a silicon compiler for high speed algorithms. EURO-DAC 1991: 436-441 - [c6]Albert van der Werf, B. T. McSweeney, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh:
Hierarchical Retiming Including Pipelining. VLSI 1991: 451-460 - 1990
- [j4]Hugo De Man, Francky Catthoor, Gert Goossens, Jan Vanhoof, Jef L. van Meerbergen, Stefaan Note, Jos A. Huisken
Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms. Proc. IEEE 78(2): 319-335 (1990) - [j3]Jef L. van Meerbergen, Jos Huisken
An integrated automatic design system for complex DSP algorithms. J. VLSI Signal Process. 1(4): 265-278 (1990) - [c5]Antoine Delaruelle, O. McArdle, Jef L. van Meerbergen, Cees Niessen:
Synthesis of delay functions in DSP compilers. EURO-DAC 1990: 68-72 - [c4]Dirk Lanneer, Francky Catthoor, Gert Goossens, Marc Pauwels, Jef L. van Meerbergen, Hugo De Man:
Open-ended system for high-level synthesis of flexible signal processors. EURO-DAC 1990: 272-276
1980 – 1989
- 1989
- [j2]Jan Decaluwe, Jan M. Rabaey, Jef L. van Meerbergen, Hugo J. De Man:
Interprocessor communication in synchronous multiprocessor digital signal processing chips. IEEE Trans. Acoust. Speech Signal Process. 37(12): 1816-1828 (1989) - [c3]Stefaan Note, Francky Catthoor, Jef L. van Meerbergen, Hugo De Man:
Definition and assignment of complex data-paths suited for high throughput applications. ICCAD 1989: 108-111 - 1988
- [j1]Francky Catthoor, Jan M. Rabaey, Gert Goossens, Jef L. van Meerbergen, Rajeev Jain, Hugo J. De Man, Joos Vandewalle:
Architectural strategies for an application-specific synchronous multiprocessor environment. IEEE Trans. Acoust. Speech Signal Process. 36(2): 265-284 (1988) - 1986
- [c2]Frans J. van Wijk, Frank P. Welten, Jef L. van Meerbergen, Jan Stoter, Jos A. Huisken
On the IC architecture and design of a 2 µm CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011. ICASSP 1986: 385-388 - 1982
- [c1]P. Zuidweg, Jef L. van Meerbergen, M. L. van der Meulen:
Custom LST chip-set for speech analysis. ICASSP 1982: 521-524
Coauthor Index
Jos Huisken
aka: Jos A. Huisken
aka: Jos A. Huisken
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