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Anand Ratna

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2010 – 2019

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2017
[i1]
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  - journals/corr/abs-1709-07241
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Suchandra Banerjee, Anand Ratna, Suchismita Roy:
Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits. CoRR abs/1709.07241 (2017)
2016
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Suchandra Banerjee, Anand Ratna, Suchismita Roy:
Satisfiability modulo theory based methodology for floorplanning in VLSI circuits. ISED 2016: 91-95

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