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Andrzej J. Strojwas
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Journal Articles
- 2013
- [j25]Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
:
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 1072-1085 (2013) - 2010
- [j24]Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi
Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 509-527 (2010) - 2005
- [j23]Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly:
Guest Editors' Introduction: DFM Drives Changes in Design Flow. IEEE Des. Test Comput. 22(3): 200-205 (2005) - 2003
- [j22]Davide Pandini, Lawrence T. Pileggi
Global and local congestion optimization in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 498-505 (2003) - 2001
- [j21]Mukund Sivaraman, Andrzej J. Strojwas:
Path delay fault diagnosis and coverage-a metric and an estimationtechnique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 440-457 (2001) - 2000
- [j20]Mukund Sivaraman, Andrzej J. Strojwas:
Primitive path delay faults: identification and their use in timinganalysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1347-1362 (2000) - [j19]Robert W. Dutton, Andrzej J. Strojwas:
Perspectives on technology and technology-driven CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12): 1544-1560 (2000) - 1999
- [j18]Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas:
An algorithm for determining repetitive patterns in very large IC layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 494-501 (1999) - 1993
- [j17]D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas:
The CDB/HCDB semiconductor wafer representation server. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2): 283-295 (1993) - [j16]Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas:
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 988-996 (1993) - 1991
- [j15]Andrzej J. Strojwas, Stephen W. Director:
An efficient algorithm for parametric fault simulation of monolithic IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 1049-1058 (1991) - [j14]Xiaowei Tian, Andrzej J. Strojwas:
Numerical integral method for diffusion modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(9): 1110-1124 (1991) - 1990
- [j13]Purnendu K. Mozumder, Andrzej J. Strojwas:
Statistical control of VLSI fabrication processes. Proc. IEEE 78(2): 436-455 (1990) - 1988
- [j12]Andrzej J. Strojwas, Stephen W. Director:
The process engineer's workbench. IEEE J. Solid State Circuits 23(2): 377-386 (1988) - 1987
- [j11]Ihao Chen, Andrzej J. Strojwas:
A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(4): 592-600 (1987) - [j10]Ihao Chen, Andrzej J. Strojwas:
Realistic Yield Simulation for VLSIC Structural Failures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 965-980 (1987) - [j9]Jacques Benkoski, Andrzej J. Strojwas:
A New Approach to Hierarchical and Statistical Timing Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1039-1052 (1987) - 1986
- [j8]Andrzej J. Strojwas:
The CMU-CAM System. IEEE Des. Test 3(1): 35-44 (1986) - [j7]Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director:
A Methodology for Worst-Case Analysis of Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(1): 104-113 (1986) - [j6]Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director:
VLSI Yield Prediction and Estimation: A Unified Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(1): 114-130 (1986) - [j5]Rahul Razdan, Andrzej J. Strojwas:
A Statistical Design Rule Developer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 508-520 (1986) - 1985
- [j4]Peter Odryna, Andrzej J. Strojwas:
PROD: A VLSI Fault Diagnosis System. IEEE Des. Test 2(6): 27-35 (1985) - [j3]Andrzej J. Strojwas, Stephen W. Director:
A Pattern Recognition Based Method for IC Failure Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(1): 76-92 (1985) - 1984
- [j2]Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director:
FABRICS II: A Statistically Based IC Fabrication Process Simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(1): 40-46 (1984) - 1982
- [j1]Wojciech Maly, Andrzej J. Strojwas:
Statistical Simulation of the IC Manufacturing Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1(3): 120-131 (1982)
Conference and Workshop Papers
- 2023
- [c50]Tomasz Brozek, Alberto A. P. Cattaneo, Larg Weiland, Michele Quarantelli, Alberto Coccoli, Sharad Saxena, Christopher Hess, Andrzej J. Strojwas:
In-Product BTI Aging Sensor for Reliability Screening and Early Detection of Material at Risk. IRPS 2023: 1-4 - 2019
- [c49]Andrzej J. Strojwas, Kelvin Doong, Dennis J. Ciplickas:
Yield and Reliability Challenges at 7nm and Below. MIXDES 2019: 52-55 - 2016
- [c48]Andrzej J. Strojwas, Jacob A. Abraham, Hong Hao, Max M. Shulaker:
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below. VTS 2016: 1-2 - 2014
- [c47]Kaushik Vaidyanathan, Lars Liebmann, Andrzej J. Strojwas, Larry T. Pileggi
Sub-20 nm design technology co-optimization for standard cell logic. ICCAD 2014: 124-131 - 2013
- [c46]Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
Automatic clustering of wafer spatial signatures. DAC 2013: 71:1-71:6 - 2011
- [c45]Andrzej J. Strojwas:
Cost effective scaling to 22nm and below technology nodes. DDECS 2011: 2 - 2010
- [c44]Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger:
Who solves the variability problem? DAC 2010: 218-219 - 2009
- [c43]Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi
Creating an affordable 22nm node using design-lithography co-optimization. DAC 2009: 95-96 - 2007
- [c42]Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki:
DFM/DFY: should you trust the surgeon or the family doctor? DATE 2007: 439-442 - 2005
- [c41]Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma:
Correlation-aware statistical timing analysis with non-gaussian delay distributions. DAC 2005: 77-82 - [c40]V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi:
Design methodology for IC manufacturability based on regular logic-bricks. DAC 2005: 353-358 - [c39]Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark:
Statistical critical path analysis considering correlations. ICCAD 2005: 699-704 - [c38]Xin Li, Jiayong Le, Lawrence T. Pileggi
Projection-based performance modeling for inter/intra-die variations. ICCAD 2005: 721-727 - [c37]Andrzej J. Strojwas:
Tutorial on DFM for physical design. ISPD 2005: 103 - [c36]Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark:
Statistical Critical Path Analysis Considering Correlations. PATMOS 2005: 364-373 - 2004
- [c35]Andreas J. Strojwas, Michael Campbell, Vassilios Gerousis, Jim Hogan, John Kibarian, Marc Levitt, Walter Ng, Dipu Pramanik, Mark Templeton:
When IC yield missed the target, who is at fault? DAC 2004: 80 - [c34]V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi
Routing architecture exploration for regular fabrics. DAC 2004: 204-207 - 2003
- [c33]Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, Kim Yaw Tong:
Exploring regular fabrics to optimize the performance-cost trade-off. DAC 2003: 782-787 - [c32]Davide Pandini, Lawrence T. Pileggi
Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI 2003: 7-10 - 2002
- [c31]Davide Pandini, Lawrence T. Pileggi
Congestion-Aware Logic Synthesis. DATE 2002: 664-671 - [c30]Davide Pandini, Lawrence T. Pileggi
Understanding and addressing the impact of wiring congestion during technology mapping. ISPD 2002: 131-136 - 2000
- [c29]Andrzej J. Strojwas:
Design for manufacturability: a path from system level to high yielding chips: embedded tutorial. ASP-DAC 2000: 375-376 - [c28]Ying Liu, Sani R. Nassif, Lawrence T. Pileggi
Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC 2000: 168-171 - [c27]N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang:
When bad things happen to good chips (panel session). DAC 2000: 736-737 - [c26]Andrzej J. Strojwas:
Design-Manufacturing Interface for 0.13 Micron and Below. ICCAD 2000: 575 - [c25]Carlo Guardiani, Andrzej J. Strojwas:
Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? ISQED 2000: 447- - 1999
- [c24]Ying Liu, Lawrence T. Pileggi
Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. DAC 1999: 201-206 - [c23]Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, Purnendu K. Mozumder, Andrzej J. Strojwas:
A New Methodology for Concurrent Technology Development and Cell Library Optimization. VLSI Design 1999: 18-25 - 1998
- [c22]Ying Liu, Lawrence T. Pileggi
ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models. DAC 1998: 469-472 - [c21]Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas:
A pattern matching algorithm for verification and analysis of very large IC layouts. ISPD 1998: 129-134 - 1997
- [c20]Mukund Sivaraman, Andrzej J. Strojwas:
Timing analysis based on primitive path delay fault identification. ICCAD 1997: 182-189 - [c19]Mukund Sivaraman, Andrzej J. Strojwas:
Primitive Path Delay Fault Identification. VLSI Design 1997: 95-100 - 1996
- [c18]Mukund Sivaraman, Andrzej J. Strojwas:
Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. ICCAD 1996: 494-501 - [c17]Andrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, Germano Nicollini, G. Crisenza, Bruno Franzini, J. Wiart:
Manufacturability of low power CMOS technology solutions. ISLPED 1996: 225-232 - [c16]Mukund Sivaraman, Andrzej J. Strojwas:
Diagnosis of parametric path delay faults. VLSI Design 1996: 412-417 - [c15]Mukund Sivaraman, Andrzej J. Strojwas:
A diagnosability metric for parametric path delay faults. VTS 1996: 316-323 - 1995
- [c14]Mukund Sivaraman, Andrzej J. Strojwas:
Test Vector Generation for Parametric Path Delay Faults. ITC 1995: 132-138 - 1994
- [c13]Vladimir A. Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director:
MONSTR: A Complete Thermal Simulator of Electronic Systems. DAC 1994: 570-575 - [c12]Mukund Sivaraman, Andrzej J. Strojwas:
Towards Incorporating Device Parameter Variations in Timing Analysis. EDAC-ETC-EUROASIC 1994: 338-342 - [c11]Kimon W. Michaels, Andrzej J. Strojwas:
Variable Accuracy Device Modeling for Event-Driven Circuit Simulation. EDAC-ETC-EUROASIC 1994: 557-561 - [c10]Jin-Qin Lu, Kimihiro Ogawa, Takehiko Adachi, Andrzej J. Strojwas:
Stochastic Interpolation Model Scheme for Statistical Circuit Design. ISCAS 1994: 125-128 - 1992
- [c9]Kimon W. Michaels, Andrzej J. Strojwas:
A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. ICCAD 1992: 254-257 - 1991
- [c8]Marko P. Chew, Andrzej J. Strojwas:
Utilizing Logic Information in Multi-Level Timing Simulation. DAC 1991: 215-218 - [c7]D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas:
A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. DAC 1991: 579-584 - [c6]Jacques Benkoski, Andrzej J. Strojwas:
The Role of Timing Verification in Layout Synthesis. DAC 1991: 612-619 - 1989
- [c5]Andrzej J. Strojwas:
Design for Manufacturability and Yield. DAC 1989: 454-459 - [c4]Jacques Benkoski, Andrzej J. Strojwas:
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. DAC 1989: 668-673 - [c3]Jacques Benkoski, Andrzej J. Strojwas:
Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. ITC 1989: 153-160 - 1986
- [c2]Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper:
Yield of VLSI circuits: myths vs. reality (panel). DAC 1986: 234-235 - 1985
- [c1]Andrzej J. Strojwas:
CMU-CAM system. DAC 1985: 319-325
Coauthor Index
aka: Larry T. Pileggi
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