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Inhak Lee

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2020 – today

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2024
[j2]
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Jeongkyun Kim, Byungho Yook, Youngo Lee, Taemin Choi, Kyuwon Choi, Chanho Lee, Juchang Lee, Hyeongcheol Kim, Seok Yun, Changhoon Do, Minwoo Kwak, Mijoung Kim, Yunrong Li, Hoyoung Tang, Jaeyoung Kim, Inhak Lee, Dongwook Seo, Sangyeop Baeck:
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology. IEEE J. Solid State Circuits 59(4): 1216-1224 (2024)
2023
[c4]
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Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck:
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology. VLSI Technology and Circuits 2023: 1-2
2022
[j1]
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Taejoong Song, Hoonki Kim, Woojin Rim, Hakchul Jung, Changnam Park, Inhak Lee, Sanghoon Baek, Jonghoon Jung:
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. IEEE J. Solid State Circuits 57(1): 236-244 (2022)
[c3]
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Inhak Lee, Dongwook Seo, Yunrong Li, Mijoung Kim, Sangyeop Baeck:
4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist Circuits. VLSI Technology and Circuits 2022: 218-219
2021
[c2]
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Sangyeop Baeck, Inhak Lee, Hoyoung Tang, Dongwook Seo, Jaeseung Choi, Taejoong Song, Jongwook Kye:
5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application. VLSI Circuits 2021: 1-2

2010 – 2019

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2019
[c1]
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Inhak Lee, Hanwool Jeong, Sangyeop Baeck, Siddharth Gupta, Changnam Park, Dongwook Seo, Jaeseung Choi, Jaeyoung Kim, Hoon Kim, Jungmyung Kang, Sunyung Jang, Daeyoung Moon, Sangshin Han, Taehyung Kim, Jaehyun Lim, Younghwan Park, Hyejin Hwang, Jeonseung Kang, Taejoong Song:
A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology. ISSCC 2019: 392-394

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