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Brian Crafton
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2020 – today
- 2024
- [j4]Ashwin Sanjay Lele
, Muya Chang
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. IEEE J. Solid State Circuits 59(1): 52-64 (2024) - [j3]Xiaoyu Sun
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1191-1205 (2024) - [c19]Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC 2024: 482-484 - [c18]Brian Crafton, Samuel D. Spetalnick, Muya Chang, Arijit Raychowdhury:
A 28nm Approximate / Binary 6T CAM for Sequence Alignment. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c17]Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Arijit Raychowdhury, Yan Fang:
Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. DAC 2023: 1-6 - [c16]Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury:
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. ISCAS 2023: 1 - [c15]Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. ISSCC 2023: 426-427 - [c14]Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c13]Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury:
Improving compute in-memory ECC reliability with successive correction. DAC 2022: 745-750 - [c12]Brian Crafton, Connor Talley
Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory. ISCAS 2022: 70-74 - [c11]Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. ISSCC 2022: 1-3 - [c10]Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. ISSCC 2022: 1-3 - 2021
- [j2]Brian Crafton
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads. IEEE Des. Test 38(1): 39-68 (2021) - [j1]Foroozan Karimzadeh
A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 751-764 (2021) - [c9]Brian Crafton, Andrew Paredes, Evan Gebhardt, Arijit Raychowdhury:
Hardware-Algorithm Co-Design Enabling Efficient Event-based Object Detection. AICAS 2021: 1-4 - [c8]Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury:
Merged Logic and Memory Fabrics for AI Workloads. ASP-DAC 2021: 305-310 - [c7]Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga
CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. A-SSCC 2021: 1-3 - [c6]Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury:
Statistical Optimization of Compute In-Memory Performance Under Device Variation. ISLPED 2021: 1-6 - [c5]Brian Crafton, Arijit Raychowdhury, Sung Kyu Lim
Automatic Generation of Translators for Packet-Based and Emerging Protocols. ISQED 2021: 488-495 - 2020
- [c4]Foroozan Karimzadeh, Ningyuan Cao, Brian Crafton, Justin Romberg, Arijit Raychowdhury:
Hardware-Aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices. ISCAS 2020: 1-5 - [c3]Brian Crafton, Samuel Spetalnick, Gauthaman Murali
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. VLSI-SOC 2020: 123-128 - [c2]Brian Crafton, Samuel Spetalnick, Gauthaman Murali
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. VLSI-SoC (Selected Papers) 2020: 323-341 - [i4]Brian Crafton, Samuel Spetalnick, Arijit Raychowdhury:
Counting Cards: Exploiting Weight and Variance Distributions for Robust Compute In-Memory. CoRR abs/2006.03117 (2020) - [i3]Brian Crafton, Samuel Spetalnick, Gauthaman Murali
Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics. CoRR abs/2008.06741 (2020)
2010 – 2019
- 2019
- [c1]Brian Crafton, Matt West, Padip Basnet, Eric Vogel, Arijit Raychowdhury:
Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment. ISLPED 2019: 1-6 - [i2]Brian Crafton, Abhinav Parihar, Evan Gebhardt, Arijit Raychowdhury:
Direct Feedback Alignment with Sparse Connections for Local Learning. CoRR abs/1903.02083 (2019) - [i1]Foroozan Karimzadeh, Ningyuan Cao, Brian Crafton, Justin Romberg, Arijit Raychowdhury:
Hardware-aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices. CoRR abs/1911.04468 (2019)
Coauthor Index
aka: Samuel D. Spetalnick
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last updated on 2024-10-18 20:31 CEST by the dblp team
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