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Lean Karlo S. Tolentino
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2020 – today
- 2024
- [j9]Chua-Chin Wang, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador:
A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process. Circuits Syst. Signal Process. 43(6): 3376-3395 (2024) - [j8]Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo:
A single-chip PFM-controlled LED driver with 0.5% illuminance variation. Microelectron. J. 147: 106167 (2024) - [j7]Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Jhih-Ying Ke, Cheng-Yao Lo, Tzung-Je Lee, Lean Karlo Santos Tolentino:
A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 4961-4972 (2024) - [j6]Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 972-976 (2024) - [c10]Cheng-Yao Lo, Lean Karlo Santos Tolentino, Jhih-Ying Ke, Jeffrey S. Walling, Yang Yi, Chua-Chin Wang:
A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process. AICAS 2024: 90-94 - [c9]Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. AICAS 2024: 95-99 - [c8]Soumika Majumder, Lean Karlo Santos Tolentino, Oliver Lexter July Alvarez Jose, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Chua-Chin Wang:
A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process. ISOCC 2024: 51-52 - 2023
- [j5]Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee:
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Syst. Signal Process. 42(4): 2283-2304 (2023) - [j4]Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang:
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. Integr. 90: 245-260 (2023) - [j3]Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang:
A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3862-3866 (2023) - [c7]Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. APCCAS 2023: 271-275 - [c6]Ralph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang:
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS. ASICON 2023: 1-5 - 2022
- [c5]Jyoshnavi Akiri, Lean Karlo S. Tolentino, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang:
A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. APCCAS 2022: 251-255 - [c4]Li Lin, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture. ISCAS 2022: 2923-2927 - 2021
- [j2]Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee:
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. Microelectron. J. 118: 105295 (2021) - [j1]Chua-Chin Wang, Lean Karlo S. Tolentino, Chia-Yi Huang, Chia-Hung Yeh:
A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2172-2185 (2021) - [c3]Tzung-Je Lee, Wen-Jian Su, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment. APCCAS 2021: 153-156
2010 – 2019
- 2019
- [c2]Lean Karlo S. Tolentino, Edmon O. Fernandez, Romeo L. Jorda, Shayne Nathalie D. Amora, Daniel Kristopher T. Bartolata, Joshua Ricart V. Sarucam, June Carlo L. Sobrepeña, Kristine Yvonne P. Sombol:
Development of an IoT-based Aquaponics Monitoring and Correction System with Temperature-Controlled Greenhouse. ISOCC 2019: 261-262 - [i3]Romeo Jorda Jr., C. Alcabasa, A. Buhay, E. C. Dela Cruz, J. P. Mendoza, A. Tolentino, Lean Karlo S. Tolentino, E. Fernandez, August Thio-ac, Jessica Velasco, Nilo Arago:
Automated Smart Wick System-Based Microfarm Using Internet of Things. CoRR abs/1911.01279 (2019) - [i2]Lean Karlo S. Tolentino, Dan Frederico P. Abacco, Mar Jun M. Siquihod:
Efficiency Improvement of Commercially Available MPPT Controllers Using Boost Converter. CoRR abs/1911.01524 (2019) - [i1]Ira C. Valenzuela, Lean Karlo S. Tolentino, Ronnie O. Serfa Juan:
Utilization of e-Nose Sensory Modality as Add-On Feature for Advanced Driver Assistance System. CoRR abs/1911.05374 (2019) - 2018
- [c1]Lean Karlo S. Tolentino, Emmanuel Justine G. Enrico, Ralph Lawrence M. Listanco, Mark Anthony M. Ramirez, Ted Lorenz U. Renon, Mark Rikko B. Samson:
Development of Fertile Egg Detection and Incubation System Using Image Processing and Automatic Candling. TENCON 2018: 701-706
Coauthor Index
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last updated on 2024-12-22 19:57 CET by the dblp team
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