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Stefano Di Matteo
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2020 – today
- 2024
- [j9]Stefano Di Matteo
, Ivan Sarno
CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms. IEEE Access 12: 25501-25511 (2024) - [j8]Nicasio Canino
HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement. IEEE Access 12: 60081-60094 (2024) - [j7]Pericle Perazzo
On hardware acceleration of quantum-resistant FOTA systems in automotive. Comput. Electr. Eng. 118: 109327 (2024) - [c7]Vasileios Tenentes, Stefano Di Matteo, Christos Zonios, Daniele Rossi, Sergio Saponara:
RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator. MOCAST 2024: 1-5 - 2023
- [j6]Stefano Di Matteo
VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library. IEEE Access 11: 72498-72508 (2023) - [j5]Federico Pacini
Innovative Plug-and-Play System for Electrification of Wheel-Chairs. IEEE Access 11: 89038-89051 (2023) - [c6]Stefano Di Matteo
A PUF-Based Secure Boot for RISC-V Architectures. ApplePies 2023: 87-94 - [c5]Pietro Nannipieri
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative. ApplePies 2023: 378-385 - [c4]Daniele Rossi, Nicasio Canino, Stefano Di Matteo
Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures. SEEDA-CECNSM 2023: 1-6 - 2022
- [j4]Luca Crocetti
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source. Entropy 24(2): 139 (2022) - [j3]Pietro Nannipieri
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 177-186 (2022) - [c3]Stefano Di Matteo
Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations. ApplePies 2022: 57-64 - 2021
- [j2]Pietro Nannipieri
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms. IEEE Access 9: 150798-150808 (2021) - [j1]Pietro Nannipieri
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative. Microprocess. Microsystems 87: 103444 (2021) - [c2]Pietro Nannipieri, Luca Baldanzi, Luca Crocetti
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes. ApplePies 2021: 31-38
2010 – 2019
- 2019
- [c1]Luca Baldanzi, Luca Crocetti
Crypto Accelerators for Power-Efficient and Real-Time on-Chip Implementation of Secure Algorithms. ICECS 2019: 775-778
Coauthor Index
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last updated on 2024-12-10 21:43 CET by the dblp team
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