A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM. - Kim, Taehwan; Sim, Changmin; Park, Seungwoo; Park, Jinwoo; Kim, Seongcheol; Shin, Hwaseok; So, Junseob; Lee, Seonbeen; Kwon, Youngwook; Kim, Chulwoo (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. - Shin, Hwaseok; Kang, Hyoshin; Choi, Yoonjae; Sim, Jincheol; Choi, Jonghyuck; Kwon, Youngwook; Park, Seungwoo; Kim, Seongcheol; Sim, Changmin; So, Junseob; Kim, Taehwan; Kim, Chulwoo (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications. - Kim, Hyunjin; Park, ChangHun; Park, Inho; Park, Taehyeong; Park, Seungwoo; Kim, Chulwoo (IEEE J. Solid State Circuits, 2024)

A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. - Choi, Jonghyuck; Choi, Yoonjae; Sim, Jincheol; Kwon, Youngwook; Park, Seungwoo; Kim, Seongcheol; Sim, Changmin; Kim, Chulwoo (IEEE J. Solid State Circuits, 2024)

A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. - Sim, Jincheol; Sim, Changmin; Park, Hyunsu; Choi, Yoonjae; Choi, Jonghyuck; Kwon, Youngwook; Park, Seungwoo; Kim, Seongcheol; Kim, Jong-Min; Lee, Ju-Hyung; Ko, Young-Chai; Kim, Chulwoo (IEEE J. Solid State Circuits, 2024)

A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. - Sim, Jincheol; Choi, Jonghyuck; Kwon, Youngwook; Park, Seungwoo; Kim, Seongcheol; Sim, Changmin; Shin, Hwaseok; So, Junseob; Lee, Seonbeen; Kim, Chulwoo (IEEE J. Solid State Circuits, 2024)

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. - Kim, Seongcheol; Sim, Jincheol; Choi, Yoonjae; Choi, Jonghyuck; Kwon, Youngwook; Park, Seungwoo; Sim, Changmin; So, Junseob; Park, Taehyeong; Kim, Chulwoo (IEEE J. Solid State Circuits, 2024)

A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces. - Kim, Seongcheol; Sim, Changmin; Sim, Jincheol; Choi, Jonghyuck; Kwon, Youngwook; Park, Seungwoo; So, Junseob; Shin, Hwaseok; Lee, Seonbeen; Kim, Chulwoo (IEEE J. Solid State Circuits, 2024)

A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces. - Choi, Yoonjae; Sim, Changmin; Choi, Jonghyuck; Sim, Jincheol; Park, Hyunsu; Kwon, Youngwook; Park, Seungwoo; Kim, Seongcheol; Kim, Chulwoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. - Kang, Hyoshin; Choi, Yoonjae; Sim, Jincheol; Choi, Jonghyuck; Kwon, Youngwook; Park, Seungwoo; Kim, Seongcheol; Sim, Changmin; Kim, Chulwoo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling. - Park, Seungwoo; Choi, Yoonjae; Choi, Jonghyuck; Sim, Jincheol; Kwon, Youngwook; Sim, Changmin; Kim, Seongcheol; Kim, Chulwoo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. - Choi, Yoonjae; Park, Hyunsu; Choi, Jonghyuck; Sim, Jincheol; Kwon, Youngwook; Park, Seungwoo; Kim, Seongcheol; Sim, Changmin; Kim, Chulwoo (IEEE J. Solid State Circuits, 2023)

A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. - Kwon, Youngwook; Park, Hyunsu; Choi, Yoonjae; Sim, Jincheol; Choi, Jonghyuck; Park, Seungwoo; Kim, Kyeong-Min; Choi, Changkyu; Jung, Hae-Kang; Kim, Chulwoo (IEEE J. Solid State Circuits, 2023)

A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. - Choi, Yoonjae; Park, Hyunsu; Choi, Jonghyuck; Sim, Jincheol; Kwon, Youngwook; Park, Seungwoo; Sim, Changmin; Kim, Chulwoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. - Choi, Jonghyuck; Choi, Yoonjae; Park, Hyunsu; Sim, Jincheol; Kwon, Youngwook; Park, Seungwoo; Kim, Seongcheol; Kim, Chulwoo (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. - Park, Seungwoo; Choi, Yoonjae; Sim, Jincheol; Choi, Jonghyuck; Park, Hyunsu; Kwon, Youngwook; Kim, Chulwoo (2023)

Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. - Choi, Jonghyuck; Choi, Yoonjae; Park, Hyunsu; Sim, Jincheol; Kwon, Youngwook; Park, Seungwoo; Kim, Chulwoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. - Kwon, Youngwook; Park, Hyunsu; Choi, Yoonjae; Sim, Jincheol; Choi, Jonghyuck; Park, Seungwoo; Kim, Chulwoo (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. - Park, Hyunsu; Sim, Jincheol; Choi, Yoonjae; Choi, Jonghyuck; Kwon, Youngwook; Park, Seungwoo; Park, Gyutae; Chung, Jinil; Kim, Kyeong-Min; Jung, Hae-Kang; Kim, Hyungsoo; Chun, Junhyun; et al. (IEEE J. Solid State Circuits, 2021)

M-folding method-based elliptic curve cryptosystem for industrial cyber-physical system. - Do, Tae Hoon; Park, Seungwoo; Lee, Jaehwan; Park, Sangoh (Int. J. Distributed Sens. Networks, 2019)