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Thomas Hollstein
Person information
- affiliation: Frankfurt University of Applied Sciences, Germany
- affiliation: Tallinn University of Technology, Estonia
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2020 – today
- 2023
- [c53]Daniel Helmer
, Heiko Hinkelmann
An Efficient Feature-based Method for People Counting. SAC 2023: 852-855 - 2021
- [c52]Madis Kerner
Triple Fixed-Point MAC Unit for Deep Learning. DATE 2021: 1404-1407 - [c51]Cesar G. Chaves
Lightweight Monitoring Scheme for Flooding DoS Attack Detection in Multi-Tenant MPSoCs. ISCAS 2021: 1-5 - 2020
- [c50]Madis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein:
An Efficient FPGA-based Architecture for Contractive Autoencoders. FCCM 2020: 230
2010 – 2019
- 2019
- [c49]Cesar G. Chaves
Detecting and Mitigating Low-and-Slow DoS Attacks in NoC-based MPSoCs. ReCoSoC 2019: 82-89 - 2018
- [c48]Karl Janson
Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS 2018: 147-152 - [c47]Cesar G. Chaves
A Distributed DoS Detection Scheme for NoC-based MPSoCs. NORCAS 2018: 1-6 - 2017
- [c46]Siavoosh Payandeh Azad, Behrad Niazmand
From online fault detection to fault management in Network-on-Chips: A ground-up approach. DDECS 2017: 48-53 - [c45]Siavoosh Payandeh Azad, Behrad Niazmand
Automated area and coverage optimization of minimal latency checkers. ETS 2017: 1-2 - [c44]Siavoosh Payandeh Azad, Behrad Niazmand
Comprehensive performance and robustness analysis of 2D turn models for network-on-chips. ISCAS 2017: 1-4 - [e2]Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis:
VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers. IFIP Advances in Information and Communication Technology 508, Springer 2017, ISBN 978-3-319-67103-1 [contents] - 2016
- [c43]Uljana Reinsalu, Siavoosh Payandeh Azad
Practicing start-up culture in teaching embedded systems. EWME 2016: 1-6 - [c42]Behrad Niazmand
Logic-based implementation of fault-tolerant routing in 3D network-on-chips. NOCS 2016: 1-8 - [c41]Siavoosh Payandeh Azad
SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints. ReCoSoC 2016: 1-6 - [c40]Jaan Raik
Foreword. VLSI-SoC 2016: 1 - [i1]Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan, Thomas Hollstein:
Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems. CoRR abs/1601.07089 (2016) - 2015
- [c39]Thomas Hollstein
NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip. DDECS 2015: 75-78 - [c38]Pietro Saltarelli, Behrad Niazmand
A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. DSD 2015: 288-292 - [c37]Pietro Saltarelli, Behrad Niazmand
A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers. NOCS 2015: 6:1-6:8 - [c36]Thomas Hollstein
Mixed-criticality NoC partitioning based on the NoCDepend dependability technique. ReCoSoC 2015: 1-8 - [c35]Pietro Saltarelli, Behrad Niazmand
Automated minimization of concurrent online checkers for Network-on-Chips. ReCoSoC 2015: 1-8 - 2014
- [c34]Yannick Le Moullec
A modular 6LoWPAN-based wireless sensor body area network for health-monitoring applications. APSIPA 2014: 1-4 - [c33]Thomas Hollstein
Motivation-driven learning processes at the example of embedded systems. EWME 2014: 3-6 - [c32]Haoyuan Ying, Klaus Hofmann, Thomas Hollstein
Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips. HPCS 2014: 516-522 - [c31]Haoyuan Ying, Thomas Hollstein
A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method. ReCoSoC 2014: 1-8 - 2013
- [j10]Haoyuan Ying, Ashok Jaiswal, Thomas Hollstein
Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies. J. Syst. Archit. 59(7): 528-542 (2013) - [j9]Faizal Arya Samman
Runtime Contention and Bandwidth-Aware Adaptive Routing Selection Strategies for Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 24(7): 1411-1421 (2013) - [c30]Haoyuan Ying, Thomas Hollstein, Klaus Hofmann:
Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems. DATE 2013: 1777-1782 - [c29]Haoyuan Ying, Thomas Hollstein
GSNoC - The comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systems. HPCS 2013: 217-223 - 2012
- [j8]Faizal Arya Samman
Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method. Microprocess. Microsystems 36(6): 449-461 (2012) - [j7]Faizal Arya Samman
Erratum to Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method Microprocessors and Microsystems (2012) 449-461. Microprocess. Microsystems 36(6): 527 (2012) - [c28]Haoyuan Ying, Ashok Jaiswal, Mohamed A. Abd El-Ghany
A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations. DDECS 2012: 83-88 - [c27]Haoyuan Ying, Kris Heid, Thomas Hollstein
A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems. NORCHIP 2012: 1-4 - [c26]Mohsin Amin, Mihkel Tagel, Gert Jervan
Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraints. ReCoSoC 2012: 1-6 - [c25]Haoyuan Ying, Thomas Hollstein
Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip. ReCoSoC 2012: 1-6 - 2011
- [j6]Faizal Arya Samman
Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip. Microprocess. Microsystems 35(3): 343-358 (2011) - [j5]Faizal Arya Samman
New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 22(4): 544-557 (2011) - [c24]Haoyuan Ying, Ashok Jaiswal, Thomas Hollstein
A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication. DSD 2011: 63-70 - [c23]Mihkel Tagel, Peeter Ellervee
Contention aware scheduling for NoC-based real-time systems. NORCHIP 2011: 1-4 - [c22]Thomas Hollstein
Invited paper: Design criteria for dependable System-on-Chip architectures. ReCoSoC 2011: 1-6 - 2010
- [j4]Faizal Arya Samman
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1067-1080 (2010)
2000 – 2009
- 2009
- [j3]Faizal Arya Samman
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management. VLSI Design 2009: 941701:1-941701:15 (2009) - 2008
- [c21]Faizal Arya Samman
Multicast Parallel Pipeline Router Architecture for Network-on-Chip. DATE 2008: 1396-1401 - [c20]Faizal Arya Samman
Flexible parallel pipeline network-on-chip based on dynamic packet identity management. IPDPS 2008: 1-8 - [p1]Manfred Glesner, Tudor Murgan, Thomas Hollstein:
Hardware Based Rapid Prototyping. Wiley Encyclopedia of Computer Science and Engineering 2008 - 2007
- [j2]Thomas Hollstein
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms. Comput. Electr. Eng. 33(4): 310-319 (2007) - 2005
- [c19]Martin K. F. Schafer, Thomas Hollstein
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. ICCAD 2005: 238-245 - [c18]Heiko Zimmer, Stefan Zink, Thomas Hollstein
Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip. IPDPS 2005 - [c17]Thomas Hollstein, Sujan Pandey, Manfred Glesner:
Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. ReCoSoC 2005: 85-92 - [c16]Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS 2005: 12-21 - [e1]Gilles Sassatelli, Manfred Glesner, Lionel Torres, Leandro Soares Indrusiak, Thomas Hollstein:
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005. Univ. Montpellier II 2005, ISBN 2-9517-4611-3 [contents] - 2004
- [c15]Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf
Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers 2004: 377-389 - [c14]Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Thomas Hollstein, Manfred Glesner:
An Asynchronous Switch Implmentation for Systems-on-a-Chip. MBMV 2004: 224-231 - [c13]Ralf Ludewig, Thomas Hollstein, Falko Schütz, Manfred Glesner:
Rapid Prototyping of an Integrated Testing and Debugging Unit. IEEE International Workshop on Rapid System Prototyping 2004: 187-192 - 2003
- [c12]Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. FPL 2003: 1111-1114 - [c11]Thomas Hollstein
Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs. VLSI-SoC (Selected Papers) 2003: 39-54 - [c10]Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner:
A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. VLSI-SOC 2003: 44-49 - 2002
- [c9]André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz
Integrated Design and Test Generation Under Internet Based Environment MOSCITO. DSD 2002: 187-195 - 2001
- [c8]Jochen Mades, Thomas Schneider, André Windisch, Thomas Hollstein
Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. MSE 2001: 2-3
1990 – 1999
- 1999
- [c7]Matthias Meixner, Jürgen Becker, Thomas Hollstein, Manfred Glesner:
Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems. MBMV 1999: 182-191 - 1998
- [c6]Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner:
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. CODES 1998: 29-33 - [c5]Claus Schneider, Martin Kayss, Thomas Hollstein
From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms. DATE 1998: 186-190 - 1997
- [c4]Thomas Hollstein
A prototyping environment for fuzzy controllers. FPL 1997: 482-490 - 1996
- [j1]Thomas Hollstein
Computer-aided design of fuzzy systems based on generic VHDL specifications. IEEE Trans. Fuzzy Syst. 4(4): 403-417 (1996) - 1995
- [c3]U. Zahm, Thomas Hollstein, Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner:
Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit. FPL 1995: 241-250 - 1994
- [c2]Thomas Hollstein, Saman K. Halgamuge, Andreas Kirschbaum, Manfred Glesner:
Rapid-Prototyping von anwendungsspezifischen Fuzzy Controllern mit Field Programmable Gate Arrays. Fuzzy Days 1994: 8-14 - 1992
- [c1]Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner:
High-level synthesis in a rapid-prototype environment for mechatronic systems. EURO-DAC 1992: 188-193
Coauthor Index
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last updated on 2024-04-24 22:47 CEST by the dblp team
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