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M. D. Arafat Kabir
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2020 – today
- 2024
- [c9]M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators. FCCM 2024: 223 - [c8]M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
IMAGine: An In-Memory Accelerated GEMV Engine Overlay. FPL 2024: 220-226 - [i4]Ehsan Kabir, M. D. Arafat Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang:
FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs. CoRR abs/2409.14023 (2024) - [i3]M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
IMAGine: An In-Memory Accelerated GEMV Engine Overlay. CoRR abs/2410.04367 (2024) - [i2]M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators. CoRR abs/2410.07546 (2024) - 2023
- [c7]M. D. Arafat Kabir, Joshua Hollis, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews:
Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays. FCCM 2023: 224 - [c6]M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews:
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? FPL 2023: 109-115 - [i1]M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews:
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? CoRR abs/2308.03914 (2023) - 2021
- [c5]M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
:
Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design. ACM Great Lakes Symposium on VLSI 2021: 135-140 - [c4]M. D. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho
Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization. VLSI-DAT 2021: 1-4 - 2020
- [c3]M. D. Arafat Kabir, Yarui Peng
Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools. ASP-DAC 2020: 351-356 - [c2]M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design. ICCAD 2020: 3:1-3:8 - [c1]M. D. Arafat Kabir, Yarui Peng:
Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study. SoCC 2020: 277-282
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