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Sezer Gören 0001
Person information
- affiliation: Yeditepe University, Istanbul, Turkey
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2020 – today
- 2023
- [c35]Yücel Çelik, Sezer Gören:
Facial Expression Recognition with Quarantine Face Masks Using a Synthetic Dataset Generator. IMPROVE 2023: 199-205 - 2022
- [j16]Emre Çiçek
, Sezer Gören
Physical activity forecasting with time series data using Android smartphone. Pervasive Mob. Comput. 82: 101567 (2022) - [c34]Suha Bayraktar
Design Principles for Interoperability of Private Blockchains. DBB 2022: 15-26 - 2021
- [j15]Emre Çiçek
Fully automated roadside parking spot detection in real time with deep learning. Concurr. Comput. Pract. Exp. 33(23) (2021) - [j14]Emre Çiçek
Smartphone power management based on ConvLSTM model. Neural Comput. Appl. 33(13): 8017-8029 (2021)
2010 – 2019
- 2019
- [j13]Vecdi Emre Levent
Tools and Techniques for Implementation of Real-time Video Processing Algorithms. J. Signal Process. Syst. 91(1): 93-113 (2019) - [c33]Abdullah Varici, Gurol Saglam, Seckin Ipek, Abdullah Yildiz, Sezer Gören, Aydin Aysu, Deniz Iskender, T. Baris Aktemur, H. Fatih Ugurdag:
Fast and Efficient Implementation of Lightweight Crypto Algorithm PRESENT on FPGA through Processor Instruction Set Extension. EWDTS 2019: 1-5 - [c32]Ibrahim Alper Koc, Tacha Serif
Indoor Mapping and Positioning using Augmented Reality. FiCloud 2019: 335-342 - [c31]Sezer Gören, Dilan Fatma Óncevarlk
On-Street Parking Spot Detection for Smart Cities. ISC2 2019: 292-295 - [c30]Y. Serhan Gener
Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions. VLSI-SoC 2019: 52-57 - [c29]Y. Serhan Gener
Semi- and Fully-Random Access LUTs for Smooth Functions. VLSI-SoC (Selected Papers) 2019: 279-306 - 2018
- [j12]Mehmet Yagmur Gök, Sezer Gören Ugurdag
Highly accurate and sensitive short read aligner. Turkish J. Electr. Eng. Comput. Sci. 26(2): 721-731 (2018) - [c28]Basak Kurt
Development of a Mobile News Reader Application Compatible with In-Vehicle Infotainment. MobiWIS 2018: 18-29 - [c27]Simge Helvaci
Improving Driver Behavior Using Gamification. MobiWIS 2018: 193-204 - [c26]Yusuf Turk, Baturay Ozcan, Sezer Gören:
Precise Vehicle Positioning for Indoor Navigation via OpenXC. VEHITS 2018: 440-445 - 2017
- [j11]Ahmet Kakacak, Aydin Emre Guzel, Ozan Cihangir, Sezer Gören
Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression. Integr. 57: 147-157 (2017) - [j10]H. Fatih Ugurdag
Hardware Division by Small Integer Constants. IEEE Trans. Computers 66(12): 2097-2110 (2017) - 2016
- [j9]Sezer Gören
Erratum to: Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection. J. Electron. Test. 32(1): 105-106 (2016) - [c25]H. Fatih Ugurdag, Anil Bayram, Vecdi Emre Levent
Efficient Combinational Circuits for Division by Small Integer Constants. ARITH 2016: 1-7 - [c24]Cemil Cem Gürsoy
On optimization of multi-cycle tests for test quality and application time. EWDTS 2016: 1-4 - [c23]Mert Büyükmihçi, Vecdi Emre Levent
Output Domain Downscaler. ISCIS 2016: 262-269 - 2015
- [j8]Sezer Gören
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection. J. Electron. Test. 31(5-6): 525-536 (2015) - [c22]Ferhat Canbay, Vecdi Emre Levent
An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays. BIBE 2015: 1-5 - [c21]Ferhat Canbay, Vecdi Emre Levent
Field programmable gate arrays implementation of Dual Tree Complex Wavelet Transform. EMBC 2015: 6026-6029 - 2014
- [j7]Bilgiday Yuce, H. Fatih Ugurdag, Sezer Gören
Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers. IEEE Trans. Computers 63(8): 1868-1881 (2014) - [c20]Anju P. Johnson
Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet. WESS 2014: 1:1-1:8 - [c19]Yusuf Turk, Onur Demir
Real Time Wireless Packet Monitoring with Raspberry Pi Sniffer. ISCIS 2014: 185-192 - 2013
- [j6]Sezer Gören
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration. Comput. Electr. Eng. 39(2): 386-397 (2013) - [c18]Bilgiday Yuce, H. Fatih Ugurdag, Sezer Gören
A Fast Circuit Topology for Finding the Maximum of N k-bit Numbers. IEEE Symposium on Computer Arithmetic 2013: 59-66 - [c17]Sezer Gören, Yusuf Turk, Ozgur Ozkurt, Abdullah Yildiz, H. Fatih Ugurdag:
Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only). FPGA 2013: 270 - [c16]Sezer Gören
Enabling difference-based dynamic partial self reconfiguration for large differences. IDT 2013: 1-6 - [c15]Mehmet Yagmur Gök, Mahmut Samil Sagiroglu, Cem Ünsalan
Reconfigurable hardware-based genome aligner using quality scores. SIU 2013: 1-4 - [c14]Mehmet Yagmur Gök, Mahmut Samil Sagiroglu, Cem Ünsalan
Programmable Hardware Based Short Read Aligner Using Phred Quality Scores. SocialCom 2013: 864-867 - [c13]Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören:
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC 2013 - [c12]H. Fatih Ugurdag, Fatih Temizkan, Sezer Gören
Generating fast logic circuits for m-select n-port Round Robin Arbitration. VLSI-SoC 2013: 260-265 - 2012
- [c11]H. Fatih Ugurdag, Ali Basaran, Taylan Akdogan, V. Ugur Güney, Sezer Gören
FPGA Based Particle Identification in High Energy Physics Experiments. ASAP 2012: 181-184 - [c10]Ali Basaran, H. Fatih Ugurdag, Taylan Akdogan, V. Ugur Güney, Sezer Gören
Ultra-fast curve fitting for pulses on FPGA. SIU 2012: 1-4 - 2011
- [j5]Sezer Gören
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort. ACM J. Emerg. Technol. Comput. Syst. 7(3): 12:1-12:16 (2011) - [c9]Sezer Gören
FPGA bitstream protection with PUFs, obfuscation, and multi-boot. ReCoSoC 2011: 1-2 - 2010
- [j4]H. Fatih Ugurdag, Sezer Gören
Gravitational pose estimation. Comput. Electr. Eng. 36(6): 1165-1180 (2010) - [c8]Sezer Gören
Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization. ETS 2010: 246 - [c7]Sezer Gören
FPGA design security with time division multiplexed PUFs. HPCS 2010: 608-614 - [c6]Sezer Gören
Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort. ISCIS 2010: 399-404
2000 – 2009
- 2009
- [j3]Sezer Gören
Optimization of Embedded Controllers Based on Redundant Transition Removal and Fault Simulation Using k-WISE Tests. J. Circuits Syst. Comput. 18(4): 647-663 (2009) - 2007
- [j2]Sezer Gören
On state reduction of incompletely specified finite state machines. Comput. Electr. Eng. 33(1): 58-69 (2007) - 2006
- [j1]Sezer Gören
Test sequence generation for controller verification and test with high coverage. ACM Trans. Design Autom. Electr. Syst. 11(4): 916-938 (2006) - [c5]H. Fatih Ugurdag, Yahya Sahin, Onur Baskirt, Soner Dedeoglu, Sezer Gören
Population-Based FPGA Solution to Mastermind Game. AHS 2006: 237-246 - 2002
- [c4]Sezer Gören
CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. DATE 2002: 248-254 - [c3]Sezer Gören, F. Joel Ferguson:
Testing Finite State Machines Based on a Structural Coverage Metric . ITC 2002: 773-780
1990 – 1999
- 1999
- [c2]Pak K. Chan, Mark J. Boyd, Sezer Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, Katsuharu Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu:
Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. FCCM 1999: 308-309 - [c1]Sezer Gören, F. Joel Ferguson:
Checking sequence generation for asynchronous sequential elements. ITC 1999: 406-413
Coauthor Index
aka: Hasan Fatih Ugurdag
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