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José L. Sánchez 0002
José Luis Sánchez Garcia
Person information
- affiliation: University of Castilla-La Mancha, Spain
Other persons with the same name
- José L. Sánchez 0001
(aka: José Luis Sánchez de la Rosa) — University of La Laguna, San Cristobal de La Laguna, Tenerife, Spain
- José L. Sánchez 0003 — Autonomous University of Guerrero, Faculty of Mathematics, Acalpulco, Mexico
- José L. Sánchez 0004 — UMI-LAFMIA CINVESTAV, Mexico City, Mexico
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2020 – today
- 2024
- [j51]María Engracia Gómez
RED-SEA Project: Towards a new-generation European interconnect. Microprocess. Microsystems 110: 105102 (2024) - [c68]Miguel Sánchez de la Rosa, Gabriel Gomez-Lopez, Francisco J. Andújar, Jesús Escudero-Sahuquillo, José L. Sánchez, Francisco J. Alfaro, Pierre-Axel Lagadec:
Quality-of-Service Provision for BXI3-Based Interconnection Networks. HOTI 2024: 20-23 - 2023
- [j50]Alberto Jiménez-Ruiz
Using graphics processing units for the efficient dynamic simulation of wind farms. Comput. Electr. Eng. 112: 109018 (2023) - [j49]Francisco J. Andújar
Energy efficient HPC network topologies with on/off links. Future Gener. Comput. Syst. 139: 126-138 (2023) - [j48]Alberto Jiménez-Ruiz
Using GPUs to simulate photovoltaic power plants: Special cases of performance loss. J. Comput. Sci. 71: 102042 (2023) - [j47]Francisco J. Andújar
Extending the VEF traces framework to model data center network workloads. J. Supercomput. 79(1): 814-831 (2023) - 2022
- [j46]Javier Cano-Cano
Providing quality of service in omni-path networks. J. Supercomput. 78(10): 12310-12343 (2022) - [c67]Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci
RED-SEA: Network Solution for Exascale Architectures. DSD 2022: 712-719 - 2021
- [j45]Javier Cano-Cano
Enabling Quality of Service Provision in Omni-Path Switches. Comput. Math. Methods 3(6) (2021) - [j44]Javier Cano-Cano
QoS provision in hierarchical and non-hierarchical switch architectures. J. Parallel Distributed Comput. 148: 138-150 (2021) - [j43]Cristina Olmedilla
DVL-Lossy: Isolating Congesting Flows to Optimize Packet Dropping in Lossy Data-Center Networks. IEEE Micro 41(1): 37-44 (2021) - [j42]Javier Cano-Cano
A methodology to enable QoS provision on InfiniBand hardware. J. Supercomput. 77(9): 9934-9946 (2021) - [j41]Juan-José Crespo
UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility. J. Supercomput. 77(11): 12826-12856 (2021) - [c66]Leandro do C. Martins, Juliana Castaneda
Supporting Efficient Assignment of Medical Resources in Cancer Treatments with Simulation-Optimization. WSC 2021: 1-12 - 2020
- [c65]Cristina Olmedilla
Optimizing Packet Dropping by Efficient Congesting-Flow Isolation in Lossy Data-Center Networks. Hot Interconnects 2020: 47-54 - [i2]Juan-José Crespo
UPR: Deadlock-Free Dynamic Network Reconfiguration by Exploiting Channel Dependency Graph Compatibility. CoRR abs/2006.02332 (2020) - [i1]Juan-José Crespo
TDSR: Transparent Distributed Segment-Based Routing. CoRR abs/2006.04549 (2020)
2010 – 2019
- 2019
- [j40]Francisco J. Andujar, Juan A. Villar
Constructing virtual 5-dimensional tori out of lower-dimensional network cards. Concurr. Comput. Pract. Exp. 31(2) (2019) - [j39]Juan-José Crespo
Silicon photonic networks: Signal loss and power challenges. Concurr. Comput. Pract. Exp. 31(21) (2019) - [j38]Francisco J. Andújar
Energy efficient torus networks with on/off links. J. Parallel Distributed Comput. 130: 37-49 (2019) - [j37]Javier Cano-Cano
Speeding up exascale interconnection network simulations with the VEF3 trace framework. J. Parallel Distributed Comput. 133: 124-135 (2019) - [j36]José L. Sánchez
Accelerating bioinspired lateral interaction in accumulative computation for real-time moving object detection with graphics processing units. Nat. Comput. 18(2): 217-227 (2019) - [j35]Aurelio Bermúdez
Optimization of lateral interaction in accumulative computation on GPU-based platform. J. Supercomput. 75(3): 1670-1685 (2019) - [c64]Juan-José Crespo
Methodology for Decoupled Simulation of SystemVerilog HDL Designs. HPCS 2019: 741-746 - 2018
- [j34]María T. López
A Finite State Machine Approach to Algorithmic Lateral Inhibition for Real-Time Motion Detection. Sensors 18(5): 1420 (2018) - [c63]Francisco J. Andujar, Salvador Coll, Marina Alonso, Juan-Miguel Martínez, Pedro López, Francisco J. Alfaro, José L. Sánchez, Raúl Martínez:
Analyzing Topology Parameters for Achieving Energy-Efficient k-ary n-cubes. HiPINEB@HPCA 2018: 24-31 - [c62]Javier Cano-Cano, Francisco J. Andujar, Francisco J. Alfaro, José L. Sánchez:
VEF3 Traces: Towards a Complete Framework for Modelling Network Workloads for Exascale Systems. HiPINEB@HPCA 2018: 32-39 - [c61]Juan Antonio Villar, German Maglione Mathey, Jesús Escudero-Sahuquillo
TopGen: A Library to Provide Simulation Tools with the Modeling of Interconnection Network Topologies. HPCS 2018: 452-459 - 2017
- [j33]Francisco J. Andujar-Munoz, Juan A. Villar-Ortiz, José Luis Sánchez Garcia, Francisco J. Alfaro-Cortes:
Applying search algorithms to obtain the optimal configuration of nDT torus nodes. Concurr. Comput. Pract. Exp. 29(13) (2017) - [j32]Roberto Uribe Paredes
An efficiency study of a pivot-based algorithm for similarity search on a heterogeneous platform. J. Supercomput. 73(1): 384-401 (2017) - [j31]Ricardo J. Barrientos
GPU-based exhaustive algorithms processing kNN queries. J. Supercomput. 73(10): 4611-4634 (2017) - [c60]Juan-José Crespo, Francisco J. Alfaro-Cortes, José L. Sánchez:
PhotoNoCs: Design Simulation Tool for Silicon Integrated Photonics Towards Exascale Systems. Euro-Par Workshops 2017: 715-724 - [c59]Francisco J. Andujar, Juan A. Villar, José L. Sánchez, Francisco J. Alfaro, José Duato, Holger Fröning:
A Case Study on Implementing Virtual 5D Torus Networks Using Network Components of Lower Dimensionality. HiPINEB@HPCA 2017: 9-16 - [c58]José L. Sánchez, Raúl Viana, María T. López
Acceleration of Moving Object Detection in Bio-Inspired Computer Vision. IWINAC (2) 2017: 364-373 - 2016
- [j30]Francisco J. Andujar, Juan A. Villar, José L. Sánchez, Francisco J. Alfaro, José Duato Marín:
Adaptive Routing for N-Dimensional Twin Torus. IEEE Trans. Computers 65(12): 3780-3786 (2016) - [j29]Francisco J. Andujar, Juan A. Villar, Francisco J. Alfaro, José L. Sánchez
An open-source family of tools to reproduce MPI-based workloads in interconnection network simulators. J. Supercomput. 72(12): 4601-4628 (2016) - 2015
- [j28]Francisco J. Andujar-Munoz, Juan A. Villar-Ortiz, José L. Sánchez, Francisco José Alfaro, José Duato:
N-Dimensional Twin Torus Topology. IEEE Trans. Computers 64(10): 2847-2861 (2015) - [j27]Juan A. Villar, Francisco J. Andujar, Francisco J. Alfaro, José L. Sánchez, José Duato:
Optimizing the configuration of combined high-radix switches. J. Supercomput. 71(7): 2614-2643 (2015) - [c57]Francisco J. Andujar, Juan A. Villar, José L. Sánchez
VEF Traces: A Framework for Modelling MPI Traffic in Interconnection Network Simulators. CLUSTER 2015: 841-848 - 2014
- [j26]Francisco J. Andujar, Juan A. Villar, José L. Sánchez
Building 3D Torus Using Low-Profile Expansion Cards. IEEE Trans. Computers 63(11): 2701-2715 (2014) - [j25]Juan A. Villar, Francisco J. Andujar, Francisco J. Alfaro, José L. Sánchez
Formalization and configuration methodology for high-radix combined switches. J. Supercomput. 69(3): 1410-1444 (2014) - [j24]Roberto Uribe Paredes
Towards an efficient static scheduling scheme for delivering queries to heterogeneous clusters in the similarity search problem. J. Supercomput. 70(2): 527-540 (2014) - [c56]Francisco J. Andújar, Juan A. Villar, Francisco J. Alfaro, José L. Sánchez, José Duato:
Deadlock-free routing mechanism for 3D twin torus networks. INA-OCMC@HiPEAC 2014: 3:1-3:4 - [c55]Francisco J. Andujar, Juan A. Villar, José L. Sánchez
Optimal Configuration for N-Dimensional Twin Torus Networks. NCA 2014: 59-66 - 2013
- [j23]Rafael Rodríguez-Sánchez
3D high definition video coding on a GPU-based heterogeneous system. Comput. Electr. Eng. 39(8): 2623-2637 (2013) - [j22]Rafael Rodríguez-Sánchez
Adapting hierarchical bidirectional inter prediction on a GPU-based platform for 2D and 3D H.264 video coding. EURASIP J. Adv. Signal Process. 2013: 67 (2013) - [j21]Juan A. Villar, Francisco J. Andujar, José L. Sánchez
Obtaining the optimal configuration of high-radix Combined switches. J. Parallel Distributed Comput. 73(9): 1239-1250 (2013) - [j20]Rafael Rodríguez-Sánchez
H.264/AVC inter prediction on accelerator-based multi-core systems. Multim. Tools Appl. 66(3): 361-381 (2013) - [j19]Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12(4): 106:1-106:29 (2013) - [j18]Rafael Rodríguez-Sánchez
H.264/AVC inter prediction for heterogeneous computing systems. J. Supercomput. 64(1): 79-88 (2013) - [j17]Juan A. Villar, Pedro Javier García
An integrated solution for QoS provision and congestion management in high-performance interconnection networks using deterministic source-based routing. J. Supercomput. 66(1): 284-304 (2013) - [c54]Rafael Rodríguez-Sánchez
Low delay H.264/AVC bidirectional inter prediction on a GPU. ICIP 2013: 2111-2115 - 2012
- [j16]Rafael Rodríguez-Sánchez
Optimizing H.264/AVC interprediction on a GPU-based framework. Concurr. Comput. Pract. Exp. 24(14): 1607-1624 (2012) - [j15]Raúl Martínez, José M. Claver
Hardware implementation study of several new egress link scheduling algorithms. J. Parallel Distributed Comput. 72(8): 975-989 (2012) - [j14]Francisco Triviño, José L. Sánchez
Network-on-Chip virtualization in Chip-Multiprocessor Systems. J. Syst. Archit. 58(3-4): 126-139 (2012) - [c53]Roberto Uribe Paredes
Improving the Performance for the Range Search on Metric Spaces Using a Multi-GPU Platform. DEXA (2) 2012: 442-449 - [c52]Rafael Rodríguez-Sánchez
A Fast GPU-Based Motion Estimation Algorithm for HD 3D Video Coding. ISPA 2012: 166-173 - [c51]Rafael Rodríguez-Sánchez
A Fast GPU-Based Motion Estimation Algorithm for H.264/AVC. MMM 2012: 551-562 - [c50]Juan A. Villar, Francisco J. Andujar, José L. Sánchez
Optimal Configuration of High-Radix Combined Switches. PDP 2012: 102-111 - [c49]Francisco Triviño, José L. Sánchez
Exploring NoC Virtualization Alternatives in CMPs. PDP 2012: 473-482 - [c48]Alessandro Strano, Davide Bertozzi, Francisco Triviño, José L. Sánchez
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. ICSAMOS 2012: 86-95 - 2011
- [j13]Francisco Triviño, José L. Sánchez
Virtualizing network-on-chip resources in chip-multiprocessors. Microprocess. Microsystems 35(2): 230-245 (2011) - [j12]Pedro Valero-Lara, José L. Sánchez
A GPU-based implementation of the MRF algorithm in ITK package. J. Supercomput. 58(3): 403-410 (2011) - [c47]Francisco Triviño, Francisco José Alfaro
A fast centralized computation routing algorithm for self-configuring NoC systems. HiPC 2011: 1-10 - [c46]Juan A. Villar, Francisco J. Andujar, José L. Sánchez
C-Switches: Increasing Switch Radix with Current Integration Scale. HPCC 2011: 40-49 - [c45]Roberto Uribe Paredes
A GPU-Based Implementation for Range Queries on Spaghettis Data Structure. ICCSA (1) 2011: 615-629 - [c44]Roberto Uribe Paredes
Similarity search implementations for multi-core and many-core processors. HPCS 2011: 656-663 - [c43]Francisco Triviño, Francisco J. Andujar, Francisco J. Alfaro, José L. Sánchez
Self-related traces: An alternative to full-system simulation for NoCs. HPCS 2011: 819-824 - [c42]Rafael Rodríguez-Sánchez
Reducing complexity in H.264/AVC motion estimation by using a GPU. MMSP 2011: 1-6 - [c41]Francisco Triviño, Francisco José Alfaro
NoC Reconfiguration for CMP Virtualization. NCA 2011: 219-222 - [c40]Juan A. Villar, Francisco J. Andujar, José L. Sánchez
Evaluation of an Alternative for Increasing Switch Radix. NCA 2011: 320-323 - 2010
- [j11]Raul Martinez-Morais, Francisco J. Alfaro-Cortes
Providing QoS with the Deficit Table Scheduler. IEEE Trans. Parallel Distributed Syst. 21(3): 327-341 (2010) - [c39]Alberto Corrales-García, Rafael Rodríguez-Sánchez
A GPU-Based DVC to H.264/AVC Transcoder. HAIS (2) 2010: 233-240
2000 – 2009
- 2009
- [j10]Francisco José Alfaro
A new strategy to manage the InfiniBand arbitration tables. J. Parallel Distributed Comput. 69(6): 508-520 (2009) - [j9]Alejandro Martínez, Pedro Javier García
A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination. IEEE Trans. Parallel Distributed Syst. 20(1): 13-24 (2009) - [c38]Raúl Martínez, Francisco José Alfaro
Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms. Euro-Par 2009: 1089-1100 - [c37]Raúl Martínez, José M. Claver
Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm. ICPP 2009: 26-33 - 2008
- [j8]Alejandro Martínez-Vicente, George Apostolopoulos, Francisco José Alfaro
Efficient Deadline-Based QoS Algorithms for High-Performance Networks. IEEE Trans. Computers 57(7): 928-939 (2008) - [j7]Raúl Martínez, Francisco José Alfaro
A Framework to Provide Quality of Service over Advanced Switching. IEEE Trans. Parallel Distributed Syst. 19(8): 1111-1123 (2008) - 2007
- [j6]Alejandro Martínez, Raúl Martínez, Francisco José Alfaro
A low-cost strategy to provide full QoS support in Advanced Switching networks. J. Syst. Archit. 53(7): 355-368 (2007) - [j5]Francisco José Alfaro
A Formal Model to Manage the InfiniBand Arbitration Tables Providing QoS. IEEE Trans. Computers 56(8): 1024-1039 (2007) - [j4]Alejandro Martínez, Francisco José Alfaro
A New Cost-Effective Technique for QoS Support in Clusters. IEEE Trans. Parallel Distributed Syst. 18(12): 1714-1726 (2007) - [c36]Alejandro Martínez-Vicente, Pedro Javier García
Integrated QoS Provision and Congestion Management for Interconnection Networks. Euro-Par 2007: 837-847 - [c35]Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato:
Providing Full QoS with 2 VCs in High-Speed Switches. ICOIN 2007: 345-354 - [c34]Raúl Martínez, Francisco José Alfaro
Comparing the latency performance of the DTable and DRR schedulers. IPDPS 2007: 1-8 - [c33]Alejandro Martínez, Francisco José Alfaro
Deadline-based QoS Algorithms for High-performance Networks. IPDPS 2007: 1-9 - [c32]Alejandro Martínez, Francisco José Alfaro
Efficient Switches with QoS Support for Clusters. IPDPS 2007: 1-6 - 2006
- [c31]Alejandro Martínez, Pedro Javier García
Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support. Euro-Par 2006: 884-895 - [c30]Raúl Martínez, Francisco José Alfaro
Improving the Flexibility of the Deficit Table Scheduler. HiPC 2006: 84-97 - [c29]Alejandro Martínez, George Apostolopoulos, Francisco José Alfaro, José L. Sánchez, José Duato:
QoS Support for Video Transmission in High-Speed Interconnects. HPCC 2006: 631-641 - [c28]Raul Martinez-Morais, Francisco J. Alfaro-Cortes
Evaluating several implementations for the AS Minimum Bandwidth Egress Link Scheduler. ICCCN 2006: 169-176 - [c27]Raúl Martínez, Francisco José Alfaro
Providing Quality of Service over Advanced Switching. ICPADS (1) 2006: 223-234 - [c26]Alejandro Martínez, Francisco José Alfaro
Scalable Low-Cost QoS Support for Single-chip Switches. ICPADS (1) 2006: 439-446 - [c25]Raúl Martínez, Francisco José Alfaro
Decoupling the Bandwidth and Latency Bounding for Table-based Schedulers. ICPP 2006: 155-163 - [c24]Raúl Martínez, Francisco José Alfaro, José L. Sánchez:
Studying Several Proposals for the Adaptation of the DTable Scheduler to Advanced Switching. ISPA 2006: 98-112 - [c23]Raúl Martínez, Francisco José Alfaro
Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler. NCA 2006: 118-125 - [c22]Alejandro Martínez, Francisco José Alfaro
Full QoS Support with 2 VCs for Single-chip Switches. NCA 2006: 239-242 - 2005
- [c21]Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato:
Providing Full QoS Support in Clusters Using Only Two VCs at the Switches. HiPC 2005: 158-169 - [c20]Francisco José Alfaro, José L. Sánchez
Studying the Influence of the InfiniBand Packet Size to Guarantee QoS. ISCC 2005: 989-994 - [c19]Raúl Martínez, José L. Sánchez
Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs. PDP 2005: 102-109 - 2004
- [j3]Francisco José Alfaro
QoS in InfiniBand Subnetworks. IEEE Trans. Parallel Distributed Syst. 15(9): 810-823 (2004) - [c18]Francisco José Alfaro, José L. Sánchez:
Tuning Buffer Size in InfiniBand to Guarantee QoS. Euro-Par 2004: 873-881 - [c17]J. E. Villalobos, José L. Sánchez, José A. Gámez, José Carlos Sancho, Antonio Robles
A Methodology to Evaluate the Effectiveness of Traffic Balancing Algorithms. Euro-Par 2004: 891-899 - [c16]Pedro Javier García, Francisco J. Quiles, Francisco José Alfaro, José L. Sánchez, José Duato:
An analysis of deadlock risk during centralized network mapping. Parallel and Distributed Computing and Networks 2004: 601-606 - 2003
- [c15]Francisco José Alfaro
A New Proposal to Fill in the InfiniBand Arbitration Tables. ICPP 2003: 133- - 2002
- [c14]Francisco José Alfaro
A Strategy to Manage Time Sensitive Traffic in InfiniBand. IPDPS 2002 - [c13]Francisco José Alfaro
A Strategy to Compute the InfiniBand Arbitration Tables. IPDPS 2002 - [c12]Pedro Javier García
Evaluation of Alternative Arbitration Policies for Myrinet Switches. IPDPS 2002 - 2001
- [j2]Rafael Casado
A Protocol for Deadlock-Free Dynamic Reconfiguration in High-Speed Local Area Networks. IEEE Trans. Parallel Distributed Syst. 12(2): 115-132 (2001) - 2000
- [j1]José L. Sánchez
Dynamic reconfiguration of node location in wormhole networks. J. Syst. Archit. 46(10): 873-888 (2000) - [c11]Francisco José Alfaro, Aurelio Bermúdez
On the Performance of Up*/Down* Routing. CANPC 2000: 61-72 - [c10]Aurelio Bermúdez
Extending Dynamic Reconfiguration to NOWs with Adaptive Routing. CANPC 2000: 73-83 - [c9]Rafael Casado, Aurelio Bermúdez, Francisco J. Quiles
Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks. HPCA 2000: 85-96
1990 – 1999
- 1999
- [c8]Rafael Casado, Francisco J. Quiles
Deadlock-Free Routing in Irregular Networks with Dynamic Reconfiguration. CANPC 1999: 165-180 - [c7]Pascual González, José L. Sánchez, Francisco José Alfaro:
An Efficient Load Balancing Method for Parallel Ray Tracing on Heterogeneous Workstation Networks. PDPTA 1999: 2622-2628 - 1998
- [c6]José L. Sánchez, José M. García, Francisco José Alfaro:
Reconfigurable Wormhole Networks: A Realistic Approach. IPPS/SPDP Workshops 1998: 428-437 - [c5]José L. Sánchez
Using channel pipelining in reconfigurable interconnection networks. PDP 1998: 120-126 - 1997
- [c4]Teresa Olivares Montes, Pedro Angel Cuenca-Castillo, Francisco José Quiles Flor
Interconnection network behavior on a multicomputer in the parallelization of the MPEG coding algorithm. Worm-hole vs. packet-switching routing. HiPC 1997: 48-53 - [c3]Francisco José Alfaro, José A. Gallud, José L. Sánchez:
A Function to Dynamic Workload Allocation in Distributed Applications. PVM/MPI 1997: 219-225 - 1996
- [c2]José M. García, José L. Sánchez, Pascual González:
PEPE: A Trace-Driven Simulator to Evaluate Reconfigurable Multicomputer Architectures. PARA 1996: 302-311 - 1995
- [c1]José L. Sánchez, José M. García, Joaquin Fernández:
Improving the Performance of Parallel Triangularization of a Sparse Matrix Using a Reconfigurable Multicomputer. PARA 1995: 493-502
Coauthor Index
Francisco J. Alfaro
aka: Francisco José Alfaro
aka: Francisco J. Alfaro-Cortes
aka: Francisco J. Alfaro-Cortés
aka: Francisco José Alfaro
aka: Francisco J. Alfaro-Cortes
aka: Francisco J. Alfaro-Cortés
[c68] [j49] [j46] [c67] [j45] [j44] [j43] [j42] [j41] [c65] [i2] [i1] [j40] [j39] [j38] [j37] [c64] [c63] [c62] [c61] [j33] [c60] [c59] [j30] [j29] [j28] [j27] [c57] [j26] [j25] [c56] [c55] [j21] [j19] [j17] [j15] [j14] [c50] [c49] [c48] [j13] [c47] [c46] [c43] [c41] [c40] [j11] [j10] [j9] [c38] [c37] [j8] [j7] [j6] [j5] [j4] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j3] [c18] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c7] [c6] [c3]
José M. Claver
aka: José Manuel Claver
aka: José Manuel Claver
José Duato
aka: José Duato Marín
aka: José Duato Marín
Francisco J. Quiles 0001
aka: Francisco José Quiles Flor
aka: Francisco José Quiles Flor
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