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Ireneusz Brzozowski
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2020 – today
- 2024
- [j4]Michal Markiewicz, Ireneusz Brzozowski, Szymon Janusz:
Spiking Neural Network Pressure Sensor. Neural Comput. 36(11): 2299-2321 (2024) - [j3]Ireneusz Brzozowski
:
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder. ACM Trans. Design Autom. Electr. Syst. 29(3): 49:1-49:22 (2024) - 2021
- [c11]Ireneusz Brzozowski:
Software Tool Aiding Analysis and Design of Low-Power Parallel Prefix Adders. MIXDES 2021: 141-146 - [i1]Piotr Rzeszut, Jakub Checinski, Ireneusz Brzozowski, Slawomir Zietek, Witold Skowronski, Tomasz Stobiecki:
Multi-state MRAM cells for hardware neuromorphic computing. CoRR abs/2102.03415 (2021) - 2020
- [c10]Ireneusz Brzozowski:
Comparative Analysis of Power Consumption of Parallel Prefix Adders. MIXDES 2020: 94-100
2010 – 2019
- 2016
- [c9]Piotr Dziurdzia, Piotr Bratek
Extraction of temperature dependent parameters for an electrothermal model of thermoelectric energy harvester. MIXDES 2016: 377-381 - 2014
- [j2]Ireneusz Brzozowski
Designing of low-power data oriented adders. Microelectron. J. 45(9): 1177-1186 (2014) - [c8]Jacek Jasielski
Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm. MIXDES 2014: 209-214 - 2013
- [c7]Ireneusz Brzozowski, Lukasz Zachara, Andrzej Kos:
Universal design method of n-to-2n decoders. MIXDES 2013: 279-284 - [c6]Ireneusz Brzozowski, Damian Palys, Andrzej Kos:
An analysis of full adder cells for low-power data oriented adders design. MIXDES 2013: 346-351
2000 – 2009
- 2008
- [j1]Ireneusz Brzozowski
A new approach to power estimation and reduction in CMOS digital circuits. Integr. 41(2): 219-237 (2008) - 2007
- [c5]Ireneusz Brzozowski
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation. DDECS 2007: 139-144 - 2005
- [c4]Ireneusz Brzozowski, Andrzej Kos:
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes. PATMOS 2005: 456-465 - 2001
- [c3]Mariusz Rawski
Practical Aspects of Logic Synthesis Based on Functional Decomposition. DSD 2001: 38-45 - 2000
- [c2]Ireneusz Brzozowski
Energy consumption minimisation with new synthesis method. ICECS 2000: 605-608
1990 – 1999
- 1999
- [c1]Ireneusz Brzozowski
Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching Activity. EUROMICRO 1999: 1376-
Coauthor Index
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last updated on 2024-11-27 21:24 CET by the dblp team
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