On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM.

Masaru Uesugi

Satoru Tanoi Yasuhiro Tokunaga Tetsuya Tanabe Kazuhiko Takahashi Atsuhiko Okada Masahiro Itoh Yoshiki Nagatomo Yoshio Ohtsuki Masaru Uesugi On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM. 1735-1742 1997 32 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.641694 db/journals/jssc/jssc32.html#TanoiTTTOINOU97

Satoru Tanoi Tetsuya Tanabe Kazuhiko Takahashi Sanpei Miyamoto Masaru Uesugi A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. 487-493 1996 31 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.499724 db/journals/jssc/jssc31.html#TanoiTTMU96

Satoru Tanoi Yasuhiro Tanaka Tetsuya Tanabe Akio Eta Toshio Inada Ryoji Hamazaki Yoshio Ohtsuki Masaru Uesugi A 32-bank 256-Mb DRAM with cache and TAG. 1330-1335 1994 November 29 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.328632 db/journals/jssc/jssc29.html#TanoiTTEIHOU94

Shizuo Chou Tsuneo Takano Akio Kita Fumio Ichikawa Masaru Uesugi A 60-ns 16-Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance. 1176-1183 1989 October 24 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/JSSC.1989.572575 db/journals/jssc/jssc24.html#ChouTKIU89 streams/journals/jssc

Shizuo Chou Akio Eta Ryoji Hamazaki Fumio Ichikawa Toshio Inada Masahiro Itoh Akio Kita Sanpei Miyamoto Yoshiki Nagatomo Yoshio Ohtsuki Atsuhiko Okada Kazuhiko Takahashi Tsuneo Takano Tetsuya Tanabe Yasuhiro Tanaka Satoru Tanoi Yasuhiro Tokunaga