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Hakan Çetinkaya
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2020 – today
- 2024
- [j2]Ezgi Palaz
, Hakan Çetinkaya
Practice-induced SNARC: evidence from a null-SNARC sample. Cogn. Process. 25(4): 601-612 (2024) - 2023
- [j1]Hakan Çetinkaya
Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm. Microelectron. J. 139: 105840 (2023) - [c5]Hakan Çetinkaya, Yasin Talay:
A Low Noise TIA with T-network Feedback Using High Value Gate Controlled PMOS Resistors. ICECS 2023: 1-4
2010 – 2019
- 2019
- [c4]Hakan Çetinkaya, Ali Zeki
Composite Resistor Technique for Process and Temperature Compensations of Low Power Ring Oscillators. LASCAS 2019: 29-32 - 2018
- [c3]Hakan Çetinkaya, Ali Zeki
A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. ICECS 2018: 277-280 - 2017
- [c2]Hakan Çetinkaya, Tufan Coskun Karalar
A concurrent multiband fully differential CMOS LNA with a local active feedback for cellular applications 3G-4G. ICECS 2017: 98-102
2000 – 2009
- 2008
- [c1]Hakan Çetinkaya, Nil Tarim:
A tunable active filter in CMOS for RF applications. ICECS 2008: 121-124
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last updated on 2025-01-09 12:50 CET by the dblp team
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