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Weng-Fai Wong
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2020 – today
- 2024
- [j61]Yujian Fu
, Cheng Chen
Optimizing the Number of Clusters for Billion-Scale Quantization-Based Nearest Neighbor Search. IEEE Trans. Knowl. Data Eng. 36(11): 6786-6800 (2024) - [j60]Zhehui Wang
Optimizing for In-Memory Deep Learning With Emerging Memory Technology. IEEE Trans. Neural Networks Learn. Syst. 35(11): 15306-15320 (2024) - [j59]Dongrui Li
1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2085-2092 (2024) - [c113]Mohit Upadhyay, Rohan Juneja, Weng-Fai Wong, Li-Shiuan Peh:
NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator. DATE 2024: 1-6 - [c112]Daniel Gerlinghoff
Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic. FPGA 2024: 235-245 - [c111]Bin Gao
IMI: In-memory Multi-job Inference Acceleration for Large Language Models. ICPP 2024: 752-761 - [c110]Kaiwen Tang, Zhanglu Yan, Weng-Fai Wong:
OneSpike: Ultra-low latency spiking neural networks. IJCNN 2024: 1-8 - [i23]Zhanglu Yan, Weiran Chu, Yuhua Sheng, Kaiwen Tang, Shida Wang, Yanfeng Liu, Weng-Fai Wong:
Integrating Deep Learning and Synthetic Biology: A Co-Design Approach for Enhancing Gene Expression via N-terminal Coding Sequences. CoRR abs/2402.13297 (2024) - [i22]Daniel Gerlinghoff, Benjamin Chen Ming Choong, Rick Siow Mong Goh, Weng-Fai Wong, Tao Luo:
Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic. CoRR abs/2403.11414 (2024) - [i21]Mohit Upadhyay, Rohan Juneja, Weng-Fai Wong, Li-Shiuan Peh:
NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator. CoRR abs/2405.04206 (2024) - [i20]Zhanglu Yan, Zhenyu Bai, Tulika Mitra, Weng-Fai Wong:
SparrowSNN: A Hardware/software Co-design for Energy Efficient ECG Classification. CoRR abs/2406.06543 (2024) - [i19]Zhanglu Yan, Zhenyu Bai, Weng-Fai Wong:
Reconsidering the energy efficiency of spiking neural networks. CoRR abs/2409.08290 (2024) - [i18]Kaiwen Tang, Zhanglu Yan, Weng-Fai Wong:
Sorbet: A Neuromorphic Hardware-Compatible Transformer-Based Spiking Language Model. CoRR abs/2409.15298 (2024) - [i17]Zhehui Wang, Tao Luo, Cheng Liu, Weichen Liu, Rick Siow Mong Goh, Weng-Fai Wong:
Enabling Energy-Efficient Deployment of Large Language Models on Memristor Crossbar: A Synergy of Large and Small. CoRR abs/2410.15977 (2024) - 2023
- [j58]Tao Luo, Weng-Fai Wong, Rick Siow Mong Goh, Anh Tuan Do, Zhixian Chen, Haizhou Li, Wenyu Jiang, Weiyun Yau:
Achieving Green AI with Energy-Efficient Deep Learning Using Neuromorphic Computing. Commun. ACM 66(7): 52-57 (2023) - [j57]Daniel Gerlinghoff
Desire backpropagation: A lightweight training algorithm for multi-layer spiking neural networks based on spike-timing-dependent plasticity. Neurocomputing 560: 126773 (2023) - [j56]Hongshi Tan
LightRW: FPGA Accelerated Graph Dynamic Random Walks. Proc. ACM Manag. Data 1(1): 90:1-90:27 (2023) - [j55]Qiange Wang
HongTu: Scalable Full-Graph GNN Training on Multiple GPUs. Proc. ACM Manag. Data 1(4): 246:1-246:27 (2023) - [j54]Zhanglu Yan
CQ$^{+}$+ Training: Minimizing Accuracy Loss in Conversion From Convolutional Neural Networks to Spiking Neural Networks. IEEE Trans. Pattern Anal. Mach. Intell. 45(10): 11600-11611 (2023) - [j53]Tian Huang
Benchmarking Quantum(-Inspired) Annealing Hardware on Practical Use Cases. IEEE Trans. Computers 72(6): 1692-1705 (2023) - [j52]Myat Thu Linn Aung
DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs. IEEE Trans. Computers 72(10): 2847-2857 (2023) - [j51]Huaipeng Zhang
Simeuro: A Hybrid CPU-GPU Parallel Simulator for Neuromorphic Computing Chips. IEEE Trans. Parallel Distributed Syst. 34(10): 2767-2782 (2023) - [c109]Nhut-Minh Ho, Duy Thanh Nguyen, John L. Gustafson, Weng-Fai Wong:
Bedot: Bit Efficient Dot Product for Deep Generative Models. CoNGA 2023: 19-37 - [c108]Himeshi De Silva, Hongshi Tan, Nhut-Minh Ho, John L. Gustafson, Weng-Fai Wong:
Towards a Better 16-Bit Number Representation for Training Neural Networks. CoNGA 2023: 114-133 - [c107]Cheng Chen, Yilin Wang, Jun Yang, Yiming Liu, Mian Lu, Zhao Zheng, Bingsheng He, Weng-Fai Wong, Liang You, Penghao Sun, Yuping Zhao, Fenghua Hu, Andy Rudoff:
OpenEmbedding: A Distributed Parameter Server for Deep Learning Recommendation Models using Persistent Memory. ICDE 2023: 2976-2987 - [c106]Bo Wang, Ming Ming Wong, Dongrui Li
1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing. ISCAS 2023: 1-5 - [c105]Zhanglu Yan, Shida Wang, Kaiwen Tang, Weng-Fai Wong:
Efficient Hyperdimensional Computing. ECML/PKDD (2) 2023: 141-155 - [i16]Zhanglu Yan, Shida Wang, Kaiwen Tang, Weng-Fai Wong
Efficient Hyperdimensional Computing. CoRR abs/2301.10902 (2023) - [i15]Hongshi Tan, Xinyu Chen, Yao Chen, Bingsheng He, Weng-Fai Wong:
LightRW: FPGA Accelerated Graph Dynamic Random Walks. CoRR abs/2304.07004 (2023) - [i14]Myat Thu Linn Aung, Daniel Gerlinghoff, Chuping Qu, Liwei Yang, Tian Huang, Rick Siow Mong Goh, Tao Luo, Weng-Fai Wong:
DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs. CoRR abs/2305.05187 (2023) - [i13]Zhanglu Yan, Shida Wang, Kaiwen Tang, Weng-Fai Wong:
HyperSNN: A new efficient and robust deep learning model for resource constrained control applications. CoRR abs/2308.08222 (2023) - [i12]Qiange Wang, Yao Chen, Weng-Fai Wong, Bingsheng He:
HongTu: Scalable Full-Graph GNN Training on Multiple GPUs (via communication-optimized CPU data offloading). CoRR abs/2311.14898 (2023) - 2022
- [j50]Liwei Yang, Huaipeng Zhang, Tao Luo
Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency. Neurocomputing 474: 128-140 (2022) - [j49]Liwei Yang, Huaipeng Zhang, Tao Luo, Chuping Qu, Myat Thu Linn Aung, Yingnan Cui, Jun Zhou, Ming Ming Wong, Junran Pu, Anh Tuan Do, Rick Siow Mong Goh, Weng-Fai Wong
Corrigendum to "Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency" [Neurocomputing (2022) 128-140]. Neurocomputing 508: 109 (2022) - [j48]Tao Luo
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2957-2969 (2022) - [j47]Nhut-Minh Ho
Tensorox: Accelerating GPU Applications via Neural Approximation on Unused Tensor Cores. IEEE Trans. Parallel Distributed Syst. 33(2): 429-443 (2022) - [j46]Xinyu Chen, Feng Cheng, Hongshi Tan, Yao Chen
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS. ACM Trans. Reconfigurable Technol. Syst. 15(4): 44:1-44:31 (2022) - [c104]Nhut-Minh Ho, Himeshi De Silva, John L. Gustafson, Weng-Fai Wong
Qtorch+: Next Generation Arithmetic for Pytorch Machine Learning. CoNGA 2022: 31-49 - [c103]Mohit Upadhyay, Rohan Juneja
REACT: a heterogeneous reconfigurable neural network accelerator with software-configurable NoCs for training and inference on wearables. DAC 2022: 1291-1296 - [c102]Bo Wang, Ke Dong, Nurul Akhira Binte Zakaria, Mohit Upadhyay, Weng-Fai Wong
Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing. ISOCC 2022: 243-244 - [c101]Xinyu Chen, Yao Chen, Feng Cheng, Hongshi Tan, Bingsheng He, Weng-Fai Wong
ReGraph: Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines. MICRO 2022: 1342-1358 - [i11]Tian Huang, Jun Xu, Tao Luo, Xiaozhe Gu, Rick Siow Mong Goh, Weng-Fai Wong:
Benchmarking Quantum(-inspired) Annealing Hardware on Practical Use Cases. CoRR abs/2203.02325 (2022) - [i10]Xinyu Chen, Yao Chen, Feng Cheng, Hongshi Tan, Bingsheng He, Weng-Fai Wong:
ReGraph: Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines. CoRR abs/2203.02676 (2022) - [i9]Daniel Gerlinghoff, Tao Luo, Rick Siow Mong Goh, Weng-Fai Wong
Desire Backpropagation: A Lightweight Training Algorithm for Multi-Layer Spiking Neural Networks based on Spike-Timing-Dependent Plasticity. CoRR abs/2211.05412 (2022) - [i8]Zhanglu Yan, Jun Zhou, Weng-Fai Wong
Low Latency Conversion of Artificial Neural Network Models to Rate-encoded Spiking Neural Networks. CoRR abs/2211.08410 (2022) - 2021
- [j45]Duy Thanh Nguyen
ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM. IEEE Access 9: 93723-93733 (2021) - [j44]Zhanglu Yan, Jun Zhou, Weng-Fai Wong
Energy efficient ECG classification with spiking neural network. Biomed. Signal Process. Control. 63: 102170 (2021) - [j43]Cheng Chen, Jun Yang, Mian Lu, Taize Wang, Zhao Zheng, Yuqiang Chen, Wenyuan Dai, Bingsheng He, Weng-Fai Wong
Optimizing An In-memory Database System For AI-powered On-line Decision Augmentation Using Persistent Memory. Proc. VLDB Endow. 14(5): 799-812 (2021) - [j42]Duy Thanh Nguyen
OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems. Sensors 21(24): 8271 (2021) - [j41]Nhut-Minh Ho
GRAM: A Framework for Dynamically Mixing Precisions in GPU Applications. ACM Trans. Archit. Code Optim. 18(2): 19:1-19:24 (2021) - [j40]Jun Zhou
Synthesis of the Dynamical Properties of Feedback Loops in Bio-Pathways. IEEE ACM Trans. Comput. Biol. Bioinform. 18(3): 1217-1226 (2021) - [c100]Zhanglu Yan, Jun Zhou, Weng-Fai Wong:
Near Lossless Transfer Learning for Spiking Neural Networks. AAAI 2021: 10577-10584 - [c99]Xinyu Chen, Hongshi Tan, Yao Chen
Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLS. DAC 2021: 937-942 - [c98]Nhut-Minh Ho
Posit Arithmetic for the Training and Deployment of Generative Adversarial Networks. DATE 2021: 1350-1355 - [c97]Xinyu Chen, Hongshi Tan, Yao Chen
ThunderGP: HLS-based Graph Processing Framework on FPGAs. FPGA 2021: 69-80 - [c96]Myat Thu Linn Aung, Chuping Qu, Liwei Yang, Tao Luo
DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays. FPL 2021: 28-32 - [c95]Hongshi Tan, Xinyu Chen, Yao Chen
ThundeRiNG: generating multiple independent random number sequences on FPGAs. ICS 2021: 115-126 - [i7]Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, Deming Chen:
Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS. CoRR abs/2105.04151 (2021) - [i6]Hongshi Tan, Xinyu Chen, Yao Chen, Bingsheng He, Weng-Fai Wong:
ThundeRiNG: Generating Multiple Independent Random Number Sequences on FPGAs. CoRR abs/2105.09578 (2021) - [i5]Tao Luo, Wai Teng Tang, Matthew Kay Fei Lee, Chuping Qu, Weng-Fai Wong, Rick Siow Mong Goh:
DTNN: Energy-efficient Inference with Dendrite Tree Inspired Neural Networks for Edge Vision Applications. CoRR abs/2105.11848 (2021) - [i4]Zhehui Wang, Tao Luo, Rick Siow Mong Goh, Wei Zhang, Weng-Fai Wong:
Optimizing for In-memory Deep Learning with Emerging Memory Technology. CoRR abs/2112.00324 (2021) - 2020
- [j39]Bokui Chen, Duo Sun, Jun Zhou, Wengfai Wong
A future intelligent traffic system with mixed autonomous vehicles and human-driven vehicles. Inf. Sci. 529: 59-72 (2020) - [j38]Cheng Chen
NV-Journaling: Locality-Aware Journaling Using Byte-Addressable Non-Volatile Memory. IEEE Trans. Computers 69(2): 288-299 (2020) - [j37]Tao Luo
An FPGA-Based Hardware Emulator for Neuromorphic Chip With RRAM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 438-450 (2020) - [c94]Xinyu Chen, Yao Chen, Ronak Bajaj, Jiong He, Bingsheng He, Weng-Fai Wong, Deming Chen:
Is FPGA Useful for Hash Joins? CIDR 2020 - [c93]Bo Wang
Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip. DATE 2020: 240-245 - [c92]Zhehui Wang
NCPower: Power Modelling for NVM-based Neuromorphic Chip. ICONS 2020: 15:1-15:7
2010 – 2019
- 2019
- [j36]Matthew Kay Fei Lee, Yingnan Cui, Thannirmalai Somu, Tao Luo
A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips. ACM Trans. Archit. Code Optim. 15(4): 64:1-64:24 (2019) - [j35]Qingchao Cai
MemepiC: Towards a Unified In-Memory Big Data Management System. IEEE Trans. Big Data 5(1): 4-17 (2019) - [j34]Jun Zhou
Fault Tolerant Stencil Computation on Cloud-Based GPU Spot Instances. IEEE Trans. Cloud Comput. 7(4): 1013-1024 (2019) - [c91]Jun Zhou, Weng-Fai Wong
Resource Efficient Personalized ECG Beat Classification via Temporal Logic Synthesis. BIBE 2019: 374-377 - [c90]Nhut-Minh Ho, Ramesh Vaddi, Weng-Fai Wong
Multi-objective Precision Optimization of Deep Neural Networks for Edge Devices. DATE 2019: 1100-1105 - [c89]Xinyu Chen, Ronak Bajaj, Yao Chen
On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAs. FPL 2019: 67-73 - [c88]Himeshi De Silva, Andrew E. Santosa, Nhut-Minh Ho, Weng-Fai Wong
ApproxSymate: path sensitive program approximation using symbolic execution. LCTES 2019: 148-162 - [p1]Weng-Fai Wong, Pooja Roy, Rajashi Ray, Nhut-Minh Ho:
Compilation and Other Software Techniques Enabling Approximate Computing. Approximate Circuits 2019: 443-463 - [i3]Bo Wang, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh:
Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip. CoRR abs/1911.10741 (2019) - 2018
- [c87]Sumanaruban Rajadurai, Jeffrey Bosboom, Weng-Fai Wong
Gloss: Seamless Live Reconfiguration and Reoptimization of Stream Programs. ASPLOS 2018: 98-112 - [c86]Himeshi De Silva, John L. Gustafson, Weng-Fai Wong
Making Strassen Matrix Multiplication Safe. HiPC 2018: 173-182 - 2017
- [c85]Nhut-Minh Ho, Elavarasi Manogaran, Weng-Fai Wong
Efficient floating point precision tuning for approximate computing. ASP-DAC 2017: 63-68 - [c84]Jun Zhou, R. Ramanathan, Weng-Fai Wong
Automated Property Synthesis of ODEs Based Bio-pathways Models. CMSB 2017: 265-282 - [c83]Nhut-Minh Ho, Weng-Fai Wong
Exploiting half precision arithmetic in Nvidia GPUs. HPEC 2017: 1-7 - [c82]Zhongle Xie, Qingchao Cai, H. V. Jagadish, Beng Chin Ooi, Weng-Fai Wong
Parallelizing Skip Lists for In-Memory Multi-Core Database Systems. ICDE 2017: 119-122 - 2016
- [j33]Chundong Wang, Weng-Fai Wong
TreeFTL: An Efficient Workload-Adaptive Algorithm for RAM Buffer Management of NAND Flash-Based Devices. IEEE Trans. Computers 65(8): 2618-2630 (2016) - [j32]Chang Yao
Exploiting Single-Threaded Model in Multi-Core In-Memory Systems. IEEE Trans. Knowl. Data Eng. 28(10): 2635-2650 (2016) - [i2]Zhongle Xie, Qingchao Cai, H. V. Jagadish, Beng Chin Ooi, Weng-Fai Wong:
PI : a Parallel in-memory skip list based Index. CoRR abs/1601.00159 (2016) - 2015
- [j31]Peera Thontirawong, Chundong Wang, Weng-Fai Wong
3DFTL: a three-level demand-based translation strategy for flash device. IEICE Electron. Express 12(8): 20150211 (2015) - [j30]Kian-Lee Tan
In-memory Databases: Challenges and Opportunities From Software and Hardware Perspectives. SIGMOD Rec. 44(2): 35-40 (2015) - [j29]N. M. Ho, N. Thoai, Weng-Fai Wong
Multi-agent simulation on multiple GPUs. Simul. Model. Pract. Theory 57: 118-132 (2015) - [j28]Wen Jun Tan, Wai Teng Tang, Rick Siow Mong Goh, Stephen John Turner
A Code Generation Framework for Targeting Optimized Library Calls for Multiple Platforms. IEEE Trans. Parallel Distributed Syst. 26(7): 1789-1799 (2015) - [j27]Wai Teng Tang, Wen Jun Tan, Rick Siow Mong Goh, Stephen John Turner
A Family of Bit-Representation-Optimized Formats for Fast Sparse Matrix-Vector Multiplication on the GPU. IEEE Trans. Parallel Distributed Syst. 26(9): 2373-2385 (2015) - [c81]Pooja Roy, Jianxing Wang, Weng-Fai Wong
PAC: Program Analysis for Approximation-aware Compilation. CASES 2015: 69-78 - [c80]R. Ramanathan, Yan Zhang, Jun Zhou, Benjamin M. Gyori
Parallelized Parameter Estimation of Biological Pathway Models. HSB 2015: 37-57 - [c79]Hao Zhang, Gang Chen, Beng Chin Ooi, Weng-Fai Wong
"Anti-Caching"-based elastic memory management for Big Data. ICDE 2015: 1268-1279 - [i1]Chang Yao, Divyakant Agrawal, Pengfei Chang, Gang Chen, Beng Chin Ooi, Weng-Fai Wong, Meihui Zhang:
DGCC: A New Dependency Graph based Concurrency Control Protocol for Multicore Database Systems. CoRR abs/1503.03642 (2015) - 2014
- [j26]Huynh Phung Huynh, Andrei Hagiescu, Zhong-Liang Ong, Weng-Fai Wong
Mapping Streaming Applications onto GPU Systems. IEEE Trans. Parallel Distributed Syst. 25(9): 2374-2385 (2014) - [j25]Zhenyu Sun, Xiuyuan Bi, Hai Li
STT-RAM Cache Hierarchy With Multiretention MTJ Designs. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1281-1293 (2014) - [c78]Jianxing Wang, Yenni Tim, Weng-Fai Wong
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. ASP-DAC 2014: 610-615 - [c77]Pooja Roy, Manmohan Manoharan, Weng-Fai Wong
EnVM: Virtual memory design for new memory architectures. CASES 2014: 12:1-12:10 - [c76]Jianxing Wang, Pooja Roy, Weng-Fai Wong
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. ICCD 2014: 133-138 - [c75]Pooja Roy, Rajarshi Ray, Chundong Wang, Weng-Fai Wong
ASAC: automatic sensitivity analysis for approximate computing. LCTES 2014: 95-104 - [c74]Jeffrey Bosboom
StreamJIT: a commensal compiler for high-performance stream programming. OOPSLA 2014: 177-195 - 2013
- [j24]Yiran Chen, Weng-Fai Wong
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM J. Emerg. Technol. Comput. Syst. 9(2): 16:1-16:22 (2013) - [j23]Andrei Hagiescu, Bing Liu
GPU code generation for ODE-based applications with phased shared-data access patterns. ACM Trans. Archit. Code Optim. 10(4): 55:1-55:19 (2013) - [c73]Chundong Wang, Weng-Fai Wong
SAW: system-assisted wear leveling on the write endurance of NAND flash devices. DAC 2013: 164:1-164:9 - [c72]Chundong Wang, Weng-Fai Wong
TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems. DATE 2013: 374-379 - [c71]Wai Teng Tang, Wen Jun Tan, Ratna Krishnamoorthy, Yi Wen Wong, Shyh-Hao Kuo, Rick Siow Mong Goh, Stephen John Turner
Optimizing and Auto-Tuning Iterative Stencil Loops for GPUs with the In-Plane Method. IPDPS 2013: 452-462 - [c70]Jianxing Wang, Yenni Tim, Weng-Fai Wong
A practical low-power memristor-based analog neural branch predictor. ISLPED 2013: 175-180 - [c69]Wai Teng Tang, Wen Jun Tan, Rajarshi Ray, Yi Wen Wong, Weiguang Chen, Shyh-Hao Kuo, Rick Siow Mong Goh, Stephen John Turner
Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes. SC 2013: 26:1-26:12 - 2012
- [j22]Bing Liu
Approximate probabilistic analysis of biopathway dynamics. Bioinform. 28(11): 1508-1516 (2012) - [c68]Chundong Wang, Weng-Fai Wong
Observational wear leveling: an efficient algorithm for flash memory management. DAC 2012: 235-242 - [c67]Chundong Wang, Weng-Fai Wong:
Extending the lifetime of NAND flash memory by salvaging bad blocks. DATE 2012: 260-263 - [c66]Yi Wen Wong, Tomasz Dubrownik, Wai Teng Tang, Wen Jun Tan, Rubing Duan, Rick Siow Mong Goh, Shyh-Hao Kuo, Stephen John Turner
Tulipse: A Visualization Framework for User-Guided Parallelization. Euro-Par 2012: 4-15 - [c65]Abdullah Al-Dujaili, Florian Deragisch, Andrei Hagiescu, Weng-Fai Wong
Guppy: A GPU-like soft-core processor. FPT 2012: 57-60 - [c64]Chandrasehar Rajaseharan, Wen Jun Tan, Wai Teng Tang, Stephen John Turner
Automatic Refactoring of Legacy Fortran Code to the Array Slicing Notation. ICPADS 2012: 698-699 - [c63]Chundong Wang, Weng-Fai Wong
ADAPT: Efficient workload-sensitive flash management based on adaptation, prediction and aggregation. MSST 2012: 1-12 - [c62]Huynh Phung Huynh, Andrei Hagiescu, Weng-Fai Wong
Scalable framework for mapping streaming applications onto multi-GPU systems. PPoPP 2012: 1-10 - [c61]Huynh Phung Huynh, Andrei Hagiescu, Weng-Fai Wong
Abstract: Mapping Streaming Applications onto GPU Systems. SC Companion 2012: 1488-1489 - [c60]Huynh Phung Huynh, Andrei Hagiescu, Weng-Fai Wong, Rick Siow Mong Goh, Abhishek Ray:
Poster: Automated Mapping Streaming Applications onto GPUs. SC Companion 2012: 1490 - 2011
- [j21]Chi-Tsai Yeh, Chun-Hao Wang, Ing-Jer Huang, Weng-Fai Wong:
Internet-based hardware/software co-design framework for embedded 3D graphics applications. EURASIP J. Adv. Signal Process. 2011: 25 (2011) - [j20]Yong Lian
Guest Editorial - BSN2010 Special Issue. IEEE Trans. Biomed. Circuits Syst. 5(4): 305-306 (2011) - [c59]Zhenxin Sun, Chi-Tsai Yeh, Weng-Fai Wong:
A UML 2-based hardware-software co-design framework for body sensor network applications. DATE 2011: 1505-1508 - [c58]Andrei Hagiescu, Weng-Fai Wong
Co-synthesis of FPGA-based application-specific floating point simd accelerators. FPGA 2011: 247-256 - [c57]Andrei Hagiescu, Huynh Phung Huynh, Weng-Fai Wong
Automated Architecture-Aware Mapping of Streaming Applications Onto GPUs. IPDPS 2011: 467-478 - [c56]Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh:
Processor caches with multi-level spin-transfer torque ram cells. ISLPED 2011: 73-78 - [c55]Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li
Multi retention level STT-RAM cache designs with a dynamic refresh scheme. MICRO 2011: 329-338 - [c54]Qin Zhao, David Koh, Syed Raza, Derek Bruening, Weng-Fai Wong
Dynamic cache contention detection in multi-threaded applications. VEE 2011: 27-38 - 2010
- [j19]Qin Zhao, Ioana Cutcutache, Weng-Fai Wong
PiPA: Pipelined profiling and analysis on multicore systems. ACM Trans. Archit. Code Optim. 7(3): 13:1-13:29 (2010) - [c53]Joon Edward Sim, Weng-Fai Wong
Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems. FCCM 2010: 179-182
2000 – 2009
- 2009
- [j18]Cheng-Kok Koh, Weng-Fai Wong
Tolerating process variations in large, set-associative caches: The buddy cache. ACM Trans. Archit. Code Optim. 6(2): 8:1-8:34 (2009) - [c52]Zhenxin Sun, Weng-Fai Wong
A UML-based approach for heterogeneous IP integration. ASP-DAC 2009: 155-160 - [c51]Ioana Cutcutache, Thi Thanh Nga Dang, Wai Kay Leong
BSN Simulator: Optimizing Application Using System Level Simulation. BSN 2009: 9-14 - [c50]Andrei Hagiescu, Weng-Fai Wong, David F. Bacon, Rodric M. Rabbah:
A computing origami: folding streams in FPGAs. DAC 2009: 282-287 - [c49]Zhiguo Ge, Tulika Mitra, Weng-Fai Wong:
A DVS-based pipelined reconfigurable instruction memory. DAC 2009: 897-902 - [c48]Joon Edward Sim, Weng-Fai Wong
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. FCCM 2009: 279-282 - [c47]Cheng-Kok Koh, Weng-Fai Wong
The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. ICCD 2009: 268-274 - [c46]Jeff H. Perkins, Sunghun Kim, Samuel Larsen, Saman P. Amarasinghe
Automatically patching errors in deployed software. SOSP 2009: 87-102 - 2008
- [j17]Ioana Cutcutache, Weng-Fai Wong
Fast, frequency-based, integrated register allocation and instruction scheduling. Softw. Pract. Exp. 38(11): 1105-1126 (2008) - [c45]Qin Zhao, Rodric M. Rabbah, Saman P. Amarasinghe, Larry Rudolph, Weng-Fai Wong
How to Do a Million Watchpoints: Efficient Debugging Using Dynamic Instrumentation. CC 2008: 147-162 - [c44]Qin Zhao, Ioana Cutcutache, Weng-Fai Wong
Pipa: pipelined profiling and analysis on multi-core systems. CGO 2008: 185-194 - [c43]Joon Edward Sim, Tulika Mitra
Defining neighborhood relations for fast spatial-temporal partitioning of applications on reconfigurable architectures. FPT 2008: 121-128 - 2007
- [j16]Gordon J. Brebner
Editorial for the Special Issue on Field Programmable Technology. J. VLSI Signal Process. 47(1): 1-2 (2007) - [c42]Rongrong Zhong, Yongxin Zhu, Weiwei Chen, Mingliang Lin, Weng-Fai Wong
An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar. AINA Workshops (1) 2007: 758-763 - [c41]Qin Zhao, Rodric M. Rabbah, Saman P. Amarasinghe, Larry Rudolph, Weng-Fai Wong
Ubiquitous Memory Introspection. CGO 2007: 299-311 - [c40]Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim:
DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems. DATE 2007: 1343-1348 - [c39]Weng-Fai Wong
VOSCH: Voltage scaled cache hierarchies. ICCD 2007: 496-503 - [c38]Kathy Dang Nguyen, P. S. Thiagarajan, Weng-Fai Wong
A UML-Based Design Framework for Time-Triggered Applications. RTSS 2007: 39-48 - 2006
- [c37]Qin Zhao, Joon Edward Sim, Weng-Fai Wong
DEP: detailed execution profile. PACT 2006: 154-163 - [c36]Yongxin Zhu, Weng-Fai Wong
Co-optimization of Performance and Power in a Superscalar Processor Design. EUC Workshops 2006: 868-878 - [c35]Y. Y. Leow, C. Y. Ng, Weng-Fai Wong
Generating hardware from OpenMP programs. FPT 2006: 73-80 - 2005
- [j15]Qin Zhao, Rodric M. Rabbah, Weng-Fai Wong:
Dynamic memory optimization using pool allocation and prefetching. SIGARCH Comput. Archit. News 33(5): 27-32 (2005) - [c34]Yongxin Zhu, Weng-Fai Wong
A Performance and Power Co-optimization Approach for Modern Processors. CIT 2005: 822-828 - [c33]Weng-Fai Wong
Targeted Data Prefetching. Asia-Pacific Computer Systems Architecture Conference 2005: 775-786 - [c32]Zhenxin Sun, Weng-Fai Wong
Design of clocked circuits using UML. ASP-DAC 2005: 901-904 - [c31]Yongxin Zhu, Weng-Fai Wong
An integrated performance and power model for superscalar processor designs. ASP-DAC 2005: 948-951 - [c30]Zhiguo Ge, Hock-Beng Lim, Weng-Fai Wong
A Reconfigurable Instruction Memory Hierarchy for Embedded Systems. FPL 2005: 7-12 - [c29]Khaing Khaing Kyi Win, Weng-Fai Wong
Cooperative Instruction Scheduling with Linear Scan Register Allocation. HiPC 2005: 528-537 - [c28]Hock-Beng Lim, Yong Meng Teo
Sensor Grid: Integration ofWireless Sensor Networks and the Grid. LCN 2005: 91-99 - [c27]Yongxin Zhu, Zhenxin Sun, Alexander Maxiaguine, Weng-Fai Wong
Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing. RTCSA 2005: 154-159 - [e1]Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong:
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singapore. IEEE 2005, ISBN 0-7803-9407-0 [contents] - 2004
- [c26]Rodric M. Rabbah, Hariharan Sandanagobalane, Mongkol Ekpanyapong, Weng-Fai Wong
Compiler orchestrated prefetching via speculation and predication. ASPLOS 2004: 189-198 - [c25]Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong
Static Identification of Delinquent Loads. CGO 2004: 303-314 - [c24]Alexander Maxiaguine, Yongxin Zhu, Samarjit Chakraborty, Weng-Fai Wong:
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs. CODES+ISSS 2004: 128-133 - [c23]Mariam Reeny George, Weng-Fai Wong:
Windows CE for a reconfigurable system-on-a-chip processor. FPT 2004: 201-207 - [c22]Lei He, Tulika Mitra
Configuration bitstream compression for dynamically reconfigurable FPGAs. ICCAD 2004: 766-773 - [c21]Jinwoo Kim, Rodric M. Rabbah, Krishna V. Palem, Weng-Fai Wong:
Adaptive Compiler Directed Prefetching for EPIC Processors. PDPTA 2004: 495-501 - [c20]Kathy Dang Nguyen, Zhenxin Sun, P. S. Thiagarajan, Weng-Fai Wong
Model-Driven SoC Design via Executable UML to SystemC. RTSS 2004: 459-468 - [c19]Chi-Hung Chi, Xiao-Yan Yu, Wenjie Zhang, Chen Ding, Weng-Fai Wong
Data Integrity Framework and Language Support for Active Web Intermediaries. WCW 2004: 94-105 - 2003
- [j14]Liang Peng, Weng-Fai Wong
SilkRoad II: mixed paradigm cluster computing with RC_dag consistency. Parallel Comput. 29(8): 1091-1115 (2003) - [c18]Liang Peng, Weng-Fai Wong
The Performance Model of SilkRoad - A Multithreaded DSM System for Clusters. CCGRID 2003: 495-501 - [c17]Jirong Liao, Weng-Fai Wong
A Model for Hardware Realization of Kernel Loops. FPL 2003: 334-344 - [c16]Zhiguo Ge, Jirong Liao, Weng-Fai Wong
Compiling to FPGAs via an EPIC compiler's intermediate representation. FPT 2003: 431-434 - 2002
- [c15]C. M. Tan, C. P. Tan, Weng-Fai Wong
Shell over a Cluster (SHOC): Towards Achieving Single System Image via the Shell. CLUSTER 2002: 28- - [c14]Liang Peng, Weng-Fai Wong
SilkRoad II: A Multi-Paradigm Runtime System for Cluster Computing. CLUSTER 2002: 443-444 - [c13]Stefan Valentin Gheorghita, Weng-Fai Wong
A co-simulation study of adaptive EPIC computing. FPT 2002: 268-275 - [c12]Shay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong
PD-XML: extensible markup language for processor description. FPT 2002: 437-440 - [c11]Jinwoo Kim, Krishna V. Palem, Weng-Fai Wong
A Framework for Data Prefetching Using Off-Line Training of Markovian Predictors. ICCD 2002: 340-347 - 2001
- [c10]Lakshmi N. Chakrapani, Pinar Korkmaz, Vincent John Mooney III, Krishna V. Palem, Kiran Puttaswamy, Weng-Fai Wong
The emerging power crisis in embedded processors: what can a poor compiler do? CASES 2001: 176-180 - [c9]Krishna V. Palem, Surendranath Talla, Weng-Fai Wong
Compiler Optimizations for Adaptive EPIC Processors. EMSOFT 2001: 257-273 - 2000
- [j13]K. S. Loh, Weng-Fai Wong
Multiple context multithreaded superscalar processor architecture. J. Syst. Archit. 46(3): 243-258 (2000) - [c8]Liang Peng, Weng-Fai Wong
SilkRoad: A Multithreaded Runtime System with Software Distributed Shared Memory for SMP Clusters. CLUSTER 2000: 243-249 - [c7]M. C. Ng, Weng-Fai Wong
ORION: An Adaptive Home-Based Software Distributed Shared Memory System. ICPADS 2000: 187-194
1990 – 1999
- 1999
- [j12]Weng-Fai Wong
Source Level Static Branch Prediction. Comput. J. 42(2): 142-149 (1999) - [j11]Weng-Fai Wong
Optimizing floating point operations in Scheme. Comput. Lang. 25(2): 89-112 (1999) - [c6]C. P. Tan, Weng-Fai Wong, Chung-Kwong Yuen:
tmPVM - Task Migratable PVM. IPPS/SPDP 1999: 196-202 - 1996
- [j10]Ming-Dong Feng, Weng-Fai Wong
BaLinda Lisp: Design and Implementation. Comput. Lang. 22(4): 205-214 (1996) - 1995
- [j9]Weng-Fai Wong
Evaluation of the Hitachi S-3800 Supercomputer Using Six Benchmarks. Int. J. High Perform. Comput. Appl. 9(1): 58-70 (1995) - [j8]Weng-Fai Wong
Fast Evaluation of the Elementary Functions in Single Precision. IEEE Trans. Computers 44(3): 453-457 (1995) - [c5]Ming-Dong Feng, Weng-Fai Wong, Chung-Kwong Yuen:
Design and Implementation of Abstract Machine for Parallel Lisp Compilation. ICPP (2) 1995: 37-44 - [c4]Ming-Dong Feng, Weng-Fai Wong, Chung-Kwong Yuen:
Highy Efficient Parallel Lisp Implementation on Distributed Systems. PARCO 1995: 319-326 - [c3]Ming-Dong Feng, Weng-Fai Wong, Chung-Kwong Yuen:
Compiling Parallel Lisp for a Shared Memory Multiprocessor. Parallel and Distributed Computing and Systems 1995: 487-490 - 1994
- [j7]Weng-Fai Wong, Eiichi Goto:
A Simulation Study on the Interactions between Multithreaded Architectures and the Cache. Int. J. High Speed Comput. 6(2): 343-356 (1994) - [j6]Weng-Fai Wong
Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers. IEEE Trans. Computers 43(3): 278-294 (1994) - [c2]Weng-Fai Wong, Eiichi Goto:
Fast Evaluation of the Elementary Functions in Double Precision. HICSS (1) 1994: 349-359 - 1992
- [j5]Paul Spee, Weng-Fai Wong
Evaluation of the continuation bit in the Cyclic Pipeline Computer. Parallel Comput. 18(12): 1349-1361 (1992) - [j4]Weng-Fai Wong, Chung-Kwong Yuen:
A Model of Speculative Parallelism. Parallel Process. Lett. 2: 265-272 (1992) - 1991
- [j3]Paul Spee, Weng-Fai Wong, Eiichi Goto:
Effects of Multiple Instruction Stream Execution on Cache Performance. Int. J. High Speed Comput. 3(2): 135-155 (1991) - 1990
- [j2]Weng-Fai Wong
A preliminary evaluation of a massively parallel processor: GAPP. Microprocessing and Microprogramming 29(1): 53-62 (1990) - [j1]Chung-Kwong Yuen, Weng-Fai Wong
A self interpreter for BaLinda Lisp. ACM SIGPLAN Notices 25(7): 39-58 (1990)
1980 – 1989
- 1989
- [c1]Weng-Fai Wong, Chung-Kwong Yuen:
BIDDLE: a bidirectional data driven Lisp engine. TAI 1989: 207-214
Coauthor Index
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