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Yoshihisa Fujimoto
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2000 – 2009
- 2009
- [j5]Yoshihisa Fujimoto:
Herman Rings of Blaschke Products of Degree 3. Int. J. Bifurc. Chaos 19(1): 445-451 (2009) - [j4]Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka:
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS. IEEE J. Solid State Circuits 44(6): 1697-1708 (2009) - 2007
- [c7]Xuefeng Chen, Yan Wang, Yoshihisa Fujimoto, Pascal Lo Ré, Yusuke Kanazawa, Jesper Steensgaard, Gabor C. Temes:
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications. CICC 2007: 73-76 - 2006
- [c6]Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto:
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique. CICC 2006: 53-56 - [c5]Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Masayuki Miyamoto:
An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers. ISSCC 2006: 201-210 - 2005
- [j3]Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto:
A delta-sigma modulator for a 1-bit digital switching amplifier. IEEE J. Solid State Circuits 40(9): 1865-1871 (2005) - 2004
- [j2]Yoshihisa Fujimoto, Hitoshi Tani, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto:
A low-power switched-capacitor variable gain amplifier. IEEE J. Solid State Circuits 39(7): 1213-1216 (2004) - [c4]Pascal Lo Ré, Yoshihisa Fujimoto, Hitoshi Tani, Masayuki Miyamoto:
A delta-sigma modulator for 1-bit digital switching amplifier [audio power amplifier]. CICC 2004: 177-180 - 2003
- [c3]Masato Koutani, Yoshihisa Fujimoto, Masayuki Miyamoto:
A highly linear CMOS buffer circuit with an adjustable output impedance. CICC 2003: 685-688 - [c2]Hitoshi Tani, Yoshihisa Fujimoto, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto:
A low power sample-and-hold amplifier. ESSCIRC 2003: 477-480 - 2001
- [j1]Kunihiko Iizuka, Masayuki Miyamoto, Yoshiji Ohta, Takahiro Suyama, Keita Hara, Shuichi Kawama, Hirofumi Matsui, Shin'ichiro Azuma, Shigenari Taguchi, Yoshihisa Fujimoto, Daniel Senderowicz:
CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops. IEEE J. Solid State Circuits 36(3): 385-397 (2001) - 2000
- [c1]Yoshihisa Fujimoto, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz:
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator. CICC 2000: 35-38
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