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Sridevan Parameswaran
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2020 – today
- 2024
- [j50]Darshana Jayasinghe, Brian Udugama, Sri Parameswaran:
1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(1): 51-86 (2024) - [j49]Sajid Hussain
, Hui Guo
MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. IEEE Trans. Dependable Secur. Comput. 21(4): 3719-3733 (2024) - [c164]Brian Udugama, Darshana Jayasinghe, Sri Parameswaran:
Sensors for Remote Power Attacks: New Developments and Challenges. ASPDAC 2024: 333-340 - [c163]Jing Gong, Hassaan Saadat, Haris Javaid, Hasindu Gamaarachchi, David Taubman, Sri Parameswaran:
SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators. DATE 2024: 1-6 - [c162]Kisaru Liyanage, Hasindu Gamaarachchi, Hassaan Saadat, Tuo Li, Hiruna Samarakoon, Sri Parameswaran:
Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions. DATE 2024: 1-6 - [c161]Mekala Bindu Bhargavi, Grandhala Sri Sai Harshith, Sri Parameswaran, Soumya J.:
Optimizing LU Decomposition with RISC-V Based Hardware Acceleration. ISVLSI 2024: 210-215 - [c160]Mekala Bindu Bhargavi, Sai Siddharth Rokkam, Sri Parameswaran, Soumya J.:
Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA. VDAT 2024: 1-6 - [e4]Francesco Regazzoni
Security, Privacy, and Applied Cryptography Engineering - 13th International Conference, SPACE 2023, Roorkee, India, December 14-17, 2023, Proceedings. Lecture Notes in Computer Science 14412, Springer 2024, ISBN 978-3-031-51582-8 [contents] - 2023
- [j48]Kisaru Liyanage
Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2924-2937 (2023) - [j47]Jing Gong
ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3505-3518 (2023) - [j46]Alberto Bosio
Special Issue: "Approximation at the Edge". ACM Trans. Embed. Comput. Syst. 22(4): 72:1-72:4 (2023) - [c159]Darshana Jayasinghe, Brian Udugama, Sri Parameswaran:
FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers. ASP-DAC 2023: 365-371 - [c158]Hasindu Gamaarachchi, Kisaru Liyanage, Sri Parameswaran:
Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis. DAC 2023: 1-4 - 2022
- [j45]Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran:
VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 657-678 (2022) - [j44]Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran
A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(4): 589-613 (2022) - [c157]Tuo Li, Sri Parameswaran:
FaSe: fast selective flushing to mitigate contention-based cache timing attacks. DAC 2022: 541-546 - [c156]Hsu-Kang Dow, Tuo Li, Sri Parameswaran:
HWST128: complete memory safety accelerator on RISC-V with metadata compression. DAC 2022: 709-714 - [i9]Tuo Li, Sri Parameswaran:
Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks. CoRR abs/2204.05508 (2022) - [i8]Jing Gong, Hassaan Saadat, Hasindu Gamaarachchi, Haris Javaid, Xiaobo Sharon Hu, Sri Parameswaran:
ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. CoRR abs/2209.04161 (2022) - [i7]Po Jui Shih, Hassaan Saadat, Sri Parameswaran, Hasindu Gamaarachchi:
Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices. CoRR abs/2211.07340 (2022) - 2021
- [j43]Darshana Jayasinghe
UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks. IEEE Access 9: 108411-108425 (2021) - [j42]Sajid Hussain
COPS: A complete oblivious processing system. Microprocess. Microsystems 85: 104295 (2021) - [j41]Darshana Jayasinghe, Aleksandar Ignjatovic, Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran:
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks. ACM Trans. Design Autom. Electr. Syst. 26(5): 33:1-33:36 (2021) - [c155]Georgios Zervakis, Hassaan Saadat, Hussam Amrouch, Andreas Gerstlauer, Sri Parameswaran, Jörg Henkel:
Approximate Computing for ML: State-of-the-art, Challenges and Visions. ASP-DAC 2021: 189-196 - [c154]Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran:
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. DAC 2021: 289-294 - 2020
- [j40]Hasindu Gamaarachchi
GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis. BMC Bioinform. 21(1): 343 (2020) - [j39]Vikkitharan Gnanasambandapillai
FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3577-3588 (2020) - [j38]Arash Bayat
Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach. IEEE ACM Trans. Comput. Biol. Bioinform. 17(1): 334-338 (2020) - [j37]Hasindu Gamaarachchi
Cache Friendly Optimisation of de Bruijn Graph Based Local Re-Assembly in Variant Calling. IEEE ACM Trans. Comput. Biol. Bioinform. 17(4): 1125-1133 (2020) - [j36]Amin Malekpour, Roshan G. Ragel, Tuo Li, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
Hardware Trojan Mitigation in Pipelined MPSoCs. ACM Trans. Design Autom. Electr. Syst. 25(1): 6:1-6:27 (2020) - [c153]Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
WEID: Worst-case Error Improvement in Approximate Dividers. ASP-DAC 2020: 593-598 - [c152]Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
REALM: Reduced-Error Approximate Log-based Integer Multiplier. DATE 2020: 1366-1371 - [c151]Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran
LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs. FPL 2020: 162-168 - [c150]Ann Franchesca Laguna
Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping. ICCAD 2020: 56:1-56:9 - [c149]Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran
A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. VLSID 2020: 84-89 - [i6]Tuo Li, Bradley Hopkins, Sri Parameswaran:
SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation. CoRR abs/2011.10249 (2020)
2010 – 2019
- 2019
- [j35]Arash Bayat
Pairwise alignment of nucleotide sequences using maximal exact matches. BMC Bioinform. 20(1): 261:1-261:15 (2019) - [j34]Ram Prasad Mohanty
SWARAM: Portable Energy and Cost Efficient Embedded System for Genomic Processing. ACM Trans. Embed. Comput. Syst. 18(5s): 61:1-61:24 (2019) - [c148]Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks. DAC 2019: 139 - [c147]Hassaan Saadat, Haris Javaid, Sri Parameswaran
Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias. DAC 2019: 161 - [c146]Amin Malekpour, Roshan G. Ragel, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran
Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing. DDECS 2019: 1-6 - [c145]Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks. ICCAD 2019: 1-7 - 2018
- [j33]Sri Parameswaran
Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). IEEE Des. Test 35(2): 101-102 (2018) - [j32]Hassaan Saadat
Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2623-2635 (2018) - [c144]Vikkitharan Gnanasambandapillai, Arash Bayat, Sri Parameswaran
MESGA: An MPSoC based embedded system solution for short read genome alignment. ASP-DAC 2018: 52-57 - [c143]Florencia Irena, Daniel Murphy, Sri Parameswaran
CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support. ASP-DAC 2018: 702-708 - [c142]Mubashir Hussain
EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip. ISVLSI 2018: 345-350 - 2017
- [j31]Arash Bayat, Bruno Gaëta, Aleksandar Ignjatovic, Sri Parameswaran
Improved VCF normalization for accurate VCF comparison. Bioinform. 33(7): 964-970 (2017) - [j30]Tao Liu, Hui Guo, Sri Parameswaran
iCETD: An improved tag generation design for memory data authentication in embedded processor systems. Integr. 56: 96-104 (2017) - [j29]Tuo Li, Muhammad Shafique
Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Trans. Computers 66(4): 647-660 (2017) - [j28]Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 296-309 (2017) - [c141]Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran
DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks. ASAP 2017: 45-52 - [c140]Hassaan Saadat, Sri Parameswaran
Hardware approximate computing: how, why, when and where? (special session). CASES 2017: 3:1-3:2 - [c139]Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran
TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs. DAC 2017: 19:1-19:6 - [c138]Sri Parameswaran
Social Presence in Social Media: Persuasion, Design and Discourse. SIGMIS-CPR 2017: 205-206 - [c137]Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks. VLSID 2017: 167-172 - [p2]Haseeb Bokhari, Sri Parameswaran
Network-on-Chip Design. Handbook of Hardware/Software Codesign 2017: 461-489 - [e3]Sri Parameswaran:
2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017. IEEE 2017, ISBN 978-1-5386-3093-8 [contents] - 2016
- [j27]Tuo Li
Processor Design for Soft Errors: Challenges and State of the Art. ACM Comput. Surv. 49(3): 57:1-57:44 (2016) - [j26]Sri Parameswaran
Editorial Introduction of New Editor-in-Chief and Associate Editors. IEEE Embed. Syst. Lett. 8(1): 1 (2016) - [j25]Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Sri Parameswaran
Switchable cache: utilising dark silicon for application specific cache optimisations. IET Comput. Digit. Tech. 10(4): 157-164 (2016) - [c136]Tao Liu, Hui Guo, Sri Parameswaran
Improving tag generation for memory data authentication in embedded processor systems. ASP-DAC 2016: 50-55 - [c135]Darshana Jayasinghe, Shivam Bhasin, Sri Parameswaran
Does it sound as it claims: a detailed side-channel security analysis of QuadSeal countermeasure. Conf. Computing Frontiers 2016: 449-454 - [c134]Tuo Li, Jude Angelo Ambrose, Sri Parameswaran:
RECORD: Reducing register traffic for checkpointing in embedded processors. DATE 2016: 582-587 - [c133]Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis. ISCAS 2016: 2018-2021 - [c132]Nastaran Nemati, Mark C. Reed, Sri Parameswaran
Self-timed automatic test pattern generation for null convention logic. MWSCAS 2016: 1-4 - [i5]Hans Michael Gerndt, Michael Glaß, Sri Parameswaran, Barry L. Rountree:
Dark Silicon: From Embedded to HPC Systems (Dagstuhl Seminar 16052). Dagstuhl Reports 6(1): 224-244 (2016) - 2015
- [j24]Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1991-2003 (2015) - [c131]Josef Schneider, Jorgen Peddersen, Sri Parameswaran
Speeding up single pass simulation of PLRUt caches. ASP-DAC 2015: 695-700 - [c130]Xi Zhang, Haris Javaid, Muhammad Shafique
ADAPT: An adaptive manycore methodology for software pipelined applications. ASP-DAC 2015: 701-706 - [c129]Darshana Jayasinghe, Aleksandar Ignjatovic, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks. CASES 2015: 21-30 - [c128]Haseeb Bokhari, Haris Javaid, Muhammad Shafique
SuperNet: multimode interconnect architecture for manycore chips. DAC 2015: 85:1-85:6 - [c127]Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran:
E-pipeline: elastic hardware/software pipelines on a many-core fabric. DATE 2015: 363-368 - [c126]Liang Tang, Jude Angelo Ambrose, Akash Kumar, Sri Parameswaran:
Dynamic reconfigurable puncturing for secure wireless communication. DATE 2015: 888-891 - [c125]Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
Malleable NoC: dark silicon inspired adaptable Network-on-Chip. DATE 2015: 1245-1248 - [c124]Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. ICCD 2015: 216-223 - [c123]Su Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran
RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. ICCD 2015: 635-642 - [c122]Jude Angelo Ambrose, Nick Higgins, Mrinal Chakravarthy, Shivam Gargg, Tuo Li, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran
ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. ISCAS 2015: 413-416 - [c121]Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power. ISCAS 2015: 3052-3055 - [c120]Jude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li, Sri Parameswaran
Side channel attacks in embedded systems: A tale of hostilities and deterrence. ISQED 2015: 452-459 - [c119]Jörg Henkel, Haseeb Bokhari, Siddharth Garg, Muhammad Usman Karim Khan, Heba Khdr
Dark Silicon: From Computation to Communication. NOCS 2015: 23:1-23:8 - [c118]Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. VLSID 2015: 29-34 - [i4]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy. CoRR abs/1506.03181 (2015) - [i3]Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran:
CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique. CoRR abs/1506.03186 (2015) - [i2]Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran:
SecureD: A Secure Dual Core Embedded Processor. CoRR abs/1511.01946 (2015) - 2014
- [b2]Haris Javaid, Sri Parameswaran
Pipelined Multiprocessor System-on-Chip for Multimedia. Springer 2014, ISBN 978-3-319-01112-7, pp. I-VIII, 1-169 - [j23]Haris Javaid, Muhammad Shafique
Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 663-676 (2014) - [j22]Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs). IEEE Trans. Parallel Distributed Syst. 25(8): 2159-2168 (2014) - [c117]Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. ASP-DAC 2014: 267-273 - [c116]Josef Schneider, Jorgen Peddersen, Sri Parameswaran
A scorchingly fast FPGA-based Precise L1 LRU cache simulator. ASP-DAC 2014: 412-417 - [c115]Muhammad Shafique
Dark silicon as a challenge for hardware/software co-design. CODES+ISSS 2014: 13:1-13:10 - [c114]Haris Javaid, Yusuke Yachide, Su Myat Min Shwe, Haseeb Bokhari, Sri Parameswaran:
FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs. DAC 2014: 33:1-33:6 - [c113]Haseeb Bokhari, Haris Javaid, Muhammad Shafique
darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon. DAC 2014: 161:1-161:6 - [c112]Josef Schneider, Jorgen Peddersen, Sri Parameswaran
MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. DAC 2014: 200:1-200:6 - [c111]Hong Chinh Doan, Haris Javaid, Sri Parameswaran:
Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. DATE 2014: 1-6 - [c110]Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran:
Hardware-based fast exploration of cache hierarchies in application specific MPSoCs. DATE 2014: 1-6 - [c109]Sri Parameswaran
Mapping programs for execution on pipelined MPSoCs. ESTIMedia 2014: 11 - [c108]Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran
Advanced modes in AES: Are they safe from power analysis based side channel attacks? ICCD 2014: 173-180 - [c107]Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
A simple digital architecture for a harmonic-cancelling sine-wave synthesizer. ISCAS 2014: 2113-2116 - [c106]Liang Tang, Jude Angelo Ambrose, Sri Parameswaran
Reconfigurable Convolutional Codec for Physical Layer Communication Security Application. MILCOM 2014: 82-87 - [i1]Shahid Mehraj Shah, Sridevan Parameswaran, Vinod Sharma:
Previous Messages Provide the Key to Achieve Shannon Capacity in a Wiretap Channel. CoRR abs/1404.5945 (2014) - 2013
- [c105]Haris Javaid, Daniel Witono, Sri Parameswaran
Multi-mode pipelined MPSoCs for streaming applications. ASP-DAC 2013: 231-236 - [c104]Su Myat Min, Haris Javaid, Sri Parameswaran
RExCache: Rapid exploration of unified last-level cache. ASP-DAC 2013: 582-587 - [c103]Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran
Run-time adaption for highly-complex multi-core systems. CODES+ISSS 2013: 13:1-13:8 - [c102]Su Myat Min, Haris Javaid, Sri Parameswaran
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs. DAC 2013: 22:1-22:10 - [c101]Tuo Li, Muhammad Shafique
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. DAC 2013: 62:1-62:7 - [c100]Liang Tang, Jude Angelo Ambrose, Sri Parameswaran
Reconfigurable pipelined coprocessor for multi-mode communication transmission. DAC 2013: 134:1-134:8 - [c99]Tuo Li, Muhammad Shafique
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. DATE 2013: 707-712 - [c98]Josef Schneider, Sri Parameswaran:
An extremely compact JPEG encoder for adaptive embedded systems. DATE 2013: 1063-1064 - [c97]Haseeb Bokhari, Haris Javaid, Sri Parameswaran
System-level optimization of on-chip communication using express links for throughput constrained MPSoCs. ESTIMedia 2013: 68-77 - [c96]Hussam Amrouch
Analyzing the thermal hotspots in FPGA-based embedded systems. FPL 2013: 1-4 - [c95]Babak Saghaie, Roshan G. Ragel, Sri Parameswaran
A novel intermittent fault Markov model for deep sub-micron processors. ACM Great Lakes Symposium on VLSI 2013: 13-18 - [c94]Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI 2013: 239-244 - [c93]Shahid Mehraj Shah
Previous messages provide the key to achieve shannon capacity in a wiretap channel. ICC Workshops 2013: 697-701 - [c92]Tuo Li, Muhammad Shafique
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. ICCAD 2013: 646-653 - [c91]Thannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra
Energy-aware synthesis of application specific MPSoCs. ICCD 2013: 62-69 - [c90]Liang Tang, Jude Angelo Ambrose, Sri Parameswaran
Variable increment step based reconfigurable interleaver for multimode communication application. ISCAS 2013: 73-76 - [c89]Jude Angelo Ambrose, Isuru Nawinne, Sri Parameswaran
Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs. ISCAS 2013: 1212-1215 - [c88]Mei Hong, Hui Guo, Sri Parameswaran
Dynamic encryption key design and management for memory data encryption in embedded systems. ISVLSI 2013: 70-75 - [c87]Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. ISVLSI 2013: 76-83 - [c86]Su Myat Min, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
A case study on exploration of last-level cache for energy reduction in DDR3 DRAM. MECO 2013: 42-45 - [c85]Liang Tang, Jude Angelo Ambrose, Sri Parameswaran
MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping. VLSI Design 2013: 1-6 - [c84]Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran
A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. VLSI Design 2013: 7-12 - 2012
- [j21]Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
Randomized Instruction Injection to Counter Power Analysis Attacks. ACM Trans. Embed. Comput. Syst. 11(3): 69:1-69:28 (2012) - [c83]Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. CODES+ISSS 2012: 151-160 - [c82]Tuo Li, Roshan G. Ragel, Sri Parameswaran:
Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. DATE 2012: 875-880 - [c81]Tuo Li, Jude Angelo Ambrose, Sri Parameswaran
Fine-grained hardware/software methodology for process migration in MPSoCs. ICCAD 2012: 508-515 - [c80]Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran
CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study. ISCAS 2012: 253-256 - [c79]Liang Tang, Jorgen Peddersen, Sri Parameswaran
A Rapid Methodology for Multi-mode Communication Circuit Generation. VLSI Design 2012: 203-208 - 2011
- [j20]Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks. IET Comput. Digit. Tech. 5(1): 1-15 (2011) - [j19]Roshan G. Ragel, Sri Parameswaran
A hybrid hardware-software technique to improve reliability in embedded processors. ACM Trans. Embed. Comput. Syst. 10(3): 36:1-36:16 (2011) - [j18]Krutartha Patel, Sri Parameswaran
Architectural Frameworks for Security and Reliability of MPSoCs. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1641-1654 (2011) - [j17]Yee Jern Chong, Sri Parameswaran
Configurable Multimode Embedded Floating-Point Units for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 2033-2044 (2011) - [c78]Haris Javaid, Muhammad Shafique, Sri Parameswaran
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study. DAC 2011: 1032-1037 - [c77]Hong Chinh Doan, Haris Javaid, Sri Parameswaran
Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos. ESTIMedia 2011: 56-65 - [c76]Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. ICCAD 2011: 126-133 - [c75]Haris Javaid, Muhammad Shafique
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. ICCAD 2011: 616-623 - [c74]Ankita Arora, Sri Parameswaran
A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks. TrustCom 2011: 1005-1014 - [c73]Su Myat Min, Jorgen Peddersen, Sri Parameswaran
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. VLSI Design 2011: 141-146 - 2010
- [j16]Xin He, Jorgen Peddersen, Sri Parameswaran
LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. Des. Autom. Embed. Syst. 14(3): 231-263 (2010) - [j15]Jörg Henkel, Sri Parameswaran
CASES 2009 guest editor's introduction. Des. Autom. Embed. Syst. 14(3): 285-286 (2010) - [j14]Hui Guo, Sri Parameswaran
Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems. J. Syst. Archit. 56(4-6): 180-190 (2010) - [j13]Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1777-1789 (2010) - [c72]Haris Javaid, Xin He, Aleksandar Ignjatovic, Sri Parameswaran
Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications. CODES+ISSS 2010: 75-84 - [c71]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC 2010: 356-361 - [c70]Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran:
Rapid runtime estimation methods for pipelined MPSoCs. DATE 2010: 363-368 - [c69]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE 2010: 496-501 - [c68]Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran:
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. DATE 2010: 920-925 - [c67]Hui Wu
Optimal WCET-aware code selection for scratchpad memory. EMSOFT 2010: 59-68 - [c66]Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
Fidelity metrics for estimation models. ICCAD 2010: 1-8 - [c65]Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. DIPES/BICC 2010: 137-144 - [c64]Xin He, Jorgen Peddersen, Sri Parameswaran
Improved Architectures for Range Encoding in Packet Classification System. NCA 2010: 10-19
2000 – 2009
- 2009
- [j12]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. IET Comput. Digit. Tech. 3(1): 94-108 (2009) - [j11]Yee Jern Chong, Sri Parameswaran
Custom Floating-Point Unit Generation for Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 638-650 (2009) - [j10]Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. ACM Trans. Design Autom. Electr. Syst. 14(2): 19:1-19:41 (2009) - [c63]Andhi Janapsatya, Sri Parameswaran
HitME: low power Hit MEmory buffer for embedded systems. ASP-DAC 2009: 335-340 - [c62]Xin He, Jorgen Peddersen, Sri Parameswaran
LOP: a novel SRAM-based architecture for low power and high throughput packet classification. CODES+ISSS 2009: 137-146 - [c61]Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. CODES+ISSS 2009: 295-304 - [c60]Haris Javaid, Sri Parameswaran
A design flow for application specific heterogeneous pipelined multiprocessor systems. DAC 2009: 250-253 - [c59]Krutartha Patel, Sri Parameswaran, Roshan G. Ragel:
CUFFS: An instruction count based architectural framework for security of MPSoCs. DATE 2009: 779-784 - [c58]Yee Jern Chong, Sri Parameswaran
Flexible multi-mode embedded floating-point unit for field programmable gate arrays. FPGA 2009: 171-180 - [c57]Xin He, Jorgen Peddersen, Sri Parameswaran
LOP_RE: Range encoding for low power packet classification. LCN 2009: 137-144 - [c56]Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran
Security and Dependability of Embedded Systems: A Computer Architects' Perspective. VLSI Design 2009: 30-32 - [e2]Jörg Henkel, Sri Parameswaran:
Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009. ACM 2009 [contents] - 2008
- [j9]Tilman Wolf
Guest editorial for special issue on embedded system security. Des. Autom. Embed. Syst. 12(3): 171-172 (2008) - [j8]Sri Parameswaran
Embedded systems security - an overview. Des. Autom. Embed. Syst. 12(3): 173-183 (2008) - [j7]Jorgen Peddersen, Sri Parameswaran
Low-Impact Processor for Dynamic Runtime Power Management. IEEE Des. Test Comput. 25(1): 52-62 (2008) - [j6]Seng Lin Shee, Andrea Erdos, Sri Parameswaran
Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG. Int. J. Parallel Program. 36(1): 140-162 (2008) - [j5]Jorgen Peddersen, Sri Parameswaran
Energy Driven Application Self-Adaptation at Run-time. J. Comput. 3(3): 14-24 (2008) - [c55]Jeremy Chan, Sri Parameswaran
NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. ASP-DAC 2008: 265-270 - [c54]Haris Javaid, Sri Parameswaran
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. CODES+ISSS 2008: 1-6 - [c53]Krutartha Patel, Sri Parameswaran
LOCS: a low overhead profiler-driven design flow for security of MPSoCs. CODES+ISSS 2008: 79-84 - [c52]Yee Jern Chong, Sri Parameswaran
Rapid application specific floating-point unit generation with bit-alignment. DAC 2008: 62-67 - [c51]Krutartha Patel, Sri Parameswaran
SHIELD: a software hardware design methodology for security and reliability of MPSoCs. DAC 2008: 858-861 - [c50]Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran
A Formal Approach To The Protocol Converter Problem. DATE 2008: 294-299 - [c49]Jude Angelo Ambrose, Sri Parameswaran
MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. ICCAD 2008: 678-684 - [c48]Jude Angelo Ambrose, Naeill Aldon, Aleksandar Ignjatovic, Sri Parameswaran
Anatomy of Differential Power Analysis for AES. SYNASC 2008: 459-466 - 2007
- [j4]Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider. IEEE Trans. Circuits Syst. II Express Briefs 54-II(4): 323-327 (2007) - [c47]Jorgen Peddersen, Sri Parameswaran
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. ASP-DAC 2007: 890-895 - [c46]Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
A smart random code injection to mask power analysis based side channel attacks. CODES+ISSS 2007: 51-56 - [c45]Krutartha Patel, Sridevan Parameswaran
Ensuring secure program execution in multiprocessor embedded systems: a case study. CODES+ISSS 2007: 57-62 - [c44]Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. DAC 2007: 489-492 - [c43]Seng Lin Shee, Sri Parameswaran
Design Methodology for Pipelined Heterogeneous Multiprocessor System. DAC 2007: 811-816 - [c42]Yee Jern Chong, Sri Parameswaran
Automatic application specific floating-point unit generation. DATE 2007: 461-466 - [c41]Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
Instruction trace compression for rapid instruction cache simulation. DATE 2007: 803-808 - [c40]Jorgen Peddersen, Sri Parameswaran
Energy Driven Application SelfAdaptation. VLSI Design 2007: 385-390 - 2006
- [j3]Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. IEEE Trans. Very Large Scale Integr. Syst. 14(8): 816-829 (2006) - [c39]Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
A novel instruction scratchpad memory optimization method based on concomitance metric. ASP-DAC 2006: 612-617 - [c38]Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
Finding optimal L1 cache configuration for embedded systems. ASP-DAC 2006: 796-801 - [c37]Roshan G. Ragel, Sri Parameswaran
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability. CODES+ISSS 2006: 100-105 - [c36]Seng Lin Shee, Andrea Erdos, Sri Parameswaran
Heterogeneous multiprocessor implementations for JPEG: : a case study. CODES+ISSS 2006: 217-222 - [c35]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. CODES+ISSS 2006: 241-246 - [c34]Roshan G. Ragel, Sri Parameswaran
IMPRES: integrated monitoring for processor reliability and security. DAC 2006: 502-505 - [c33]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Customization of application specific heterogeneous multi-pipeline processors. DATE 2006: 746-751 - [c32]Hui Wu, Sridevan Parameswaran:
Minimising the Energy Consumption of Real-Time Tasks with Precedence Constraints on a Single Processor. EUC 2006: 45-56 - [c31]Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. VLSI Design 2006: 575-580 - 2005
- [j2]Sri Parameswaran
Instruction code mapping for performance increase and energy reduction in embedded computer systems. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 498-502 (2005) - [c30]Newton Cheung, Sri Parameswaran, Jörg Henkel:
Battery-aware instruction generation for embedded processors. ASP-DAC 2005: 553-556 - [c29]Roshan G. Ragel, Sri Parameswaran
Micro embedded monitoring for security in application specific instruction-set processors. CASES 2005: 304-314 - [c28]Seng Lin Shee, Sri Parameswaran
Novel architecture for loop acceleration: a case study. CODES+ISSS 2005: 297-302 - [c27]Jeremy Chan, Sri Parameswaran
NoCEE: energy macro-model extraction methodology for network on chip routers. ICCAD 2005: 254-259 - [c26]Hui Guo, Sri Parameswaran
Balancing System Level Pipelines with Stage Voltage Scaling. ISVLSI 2005: 287-289 - [c25]Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran
Rapid Embedded Hardware/Software System Generation. VLSI Design 2005: 111-116 - [c24]Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band. WCNC 2005: 776-781 - 2004
- [c23]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Dual-pipeline heterogeneous ASIP design. CODES+ISSS 2004: 12-17 - [c22]Newton Cheung, Sri Parameswaran
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. DATE 2004: 1020-1027 - [c21]Newton Cheung, Sri Parameswaran, Jörg Henkel:
A quantitative study and estimation models for extensible instructions in embedded processors. ICCAD 2004: 183-189 - [c20]Andhi Janapsatya, Sri Parameswaran
Hardware/software managed scratchpad memory for embedded system. ICCAD 2004: 370-377 - [c19]Jeremy Chan, Sri Parameswaran
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. VLSI Design 2004: 717-720 - 2003
- [c18]Sri Parameswaran
Multi-parametric improvements for embedded systems using code-placement and address bus coding. ASP-DAC 2003: 15-21 - [c17]Newton Cheung, Jörg Henkel, Sri Parameswaran:
Rapid Configuration and Instruction Selection for an ASIP: A Case Study. DATE 2003: 10802-10809 - [c16]Newton Cheung, Sri Parameswaran, Jörg Henkel:
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. ICCAD 2003: 291-298 - [c15]Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran:
Specification and Design of Multi-Million Gate SOCs. VLSI Design 2003: 18-19 - [p1]Newton Cheung, Jörg Henkel, Sri Parameswaran:
Rapid Configuration & Instruction Selection for an ASIP: A Case Study. Embedded Software for SoC 2003: 403-417 - 2002
- [c14]Tony Han, Sri Parameswaran
SWASAD: An ASIC Design for High Speed DNA Sequence Matching. ASP-DAC/VLSI Design 2002: 541-546 - [e1]Jörg Henkel, Xiaobo Sharon Hu, Rajesh Gupta, Sri Parameswaran:
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002. ACM 2002, ISBN 1-58113-542-4 [contents] - 2001
- [c13]Sri Parameswaran
Code placement in hardware/software co-synthesis to improve performance and reduce cost. DATE 2001: 626-632 - [c12]Sri Parameswaran
I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. ICCAD 2001: 635- - 2000
- [j1]Sri Parameswaran
Profiling in the ASP codesign environment. J. Syst. Archit. 46(14): 1263-1274 (2000) - [c11]Allan Rae, Sri Parameswaran
Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. ASP-DAC 2000: 147-152 - [c10]Vince E. Boros, Aleksandar D. Rakic
High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. DAC 2000: 221-226
1990 – 1999
- 1998
- [c9]Sri Parameswaran:
HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). ASP-DAC 1998: 19-22 - [c8]Hui Guo, Sri Parameswaran:
Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. ASP-DAC 1998: 99-104 - [c7]Sri Parameswaran, Hui Guo:
Power Reduction in Pipelines. ASP-DAC 1998: 545-550 - [c6]Allan Rae, Sri Parameswaran:
Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. ISSS 1998: 83-88 - 1997
- [c5]Sri Parameswaran, Hui Guo:
Power consumption in CMOS combinational logic blocks at high frequencies. ASP-DAC 1997: 195-200 - 1995
- [c4]Pradip K. Jha, Nikil D. Dutt
Reclocking for high-level synthesis. ASP-DAC 1995 - [c3]Matthew F. Parkinson, Sri Parameswaran:
Profiling in the ASP codesign environment. ISSS 1995: 128-133 - 1994
- [c2]Sayed Mohammad Kia, Sri Parameswaran:
Design automation of self checking circuits. EURO-DAC 1994: 252-257 - [c1]Sayed Mohammad Kia, Sri Parameswaran:
Novel architectures for TSC/CD and SFS/SCD synchronous controllers. VTS 1994: 138-143 - 1991
- [b1]Sridevan Parameswaran
SPOT: A computer aided digital design system. University of Queensland, Australia, 1991
Coauthor Index
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