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Yuh-Kuang Tseng

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2000 – 2009

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2007
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Yuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng:
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. SoCC 2007: 277-280
2006
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Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng:
A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. ISCAS 2006

1990 – 1999

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1999
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Yuh-Kuang Tseng, Chung-Yu Wu:
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications. IEEE J. Solid State Circuits 34(1): 68-79 (1999)
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Yuh-Kuang Tseng:
SRAM. The VLSI Handbook 1999
1998
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Yuh-Kuang Tseng, Chung-Yu Wu:
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications. IEEE J. Solid State Circuits 33(10): 1576-1579 (1998)
1996
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Chung-Yu Wu, Yuh-Kuang Tseng:
Bipolar bootstrapped multi-emitter BiCMOS (B²M-BiCMOS) logic for low-voltage applications. ICECS 1996: 1174-1177
1994
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Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu:
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. ISCAS 1994: 23-26

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