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Heiner Giefers
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2010 – 2019
- 2018
- [j5]Raphael Polig, Kubilay Atasu
, Heiner Giefers
A hardware compilation framework for text analytics queries. J. Parallel Distributed Comput. 111: 260-272 (2018) - [c18]Dionysios Diamantopoulos, Heiner Giefers
ecTALK: Energy efficient coherent transprecision accelerators - The bidirectional long short-term memory neural network case. COOL CHIPS 2018: 1-3 - [c17]Heiner Giefers
Extending the POWER Architecture with Transprecision Co-Processors. ISCAS 2018: 1-5 - 2016
- [j4]Christoph M. Angerer, Raphael Polig, D. Zegarac, Heiner Giefers
A fast, hybrid, power-efficient high-precision solver for large linear systems based on low-precision hardware. Sustain. Comput. Informatics Syst. 12: 72-82 (2016) - [j3]Heiner Giefers
Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT. J. Signal Process. Syst. 85(3): 307-323 (2016) - [c16]Heiner Giefers
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA. FPL 2016: 1-9 - [c15]Peter W. J. Staar, Panagiotis Kl. Barkoutsos, Roxana Istrate, A. Cristiano I. Malossi
Stochastic Matrix-Function Estimators: Scalable Big-Data Kernels with High Performance. IPDPS 2016: 812-821 - [c14]Heiner Giefers
Analyzing the energy-efficiency of sparse matrix multiplication on heterogeneous systems: A comparative study of GPU, Xeon Phi and FPGA. ISPASS 2016: 46-56 - [c13]Giorgis Georgakoudis
NanoStreams: Codesigned microservers for edge analytics in real time. SAMOS 2016: 180-187 - 2015
- [c12]Raphael Polig, Heiner Giefers
A soft-core processor array for relational operators. ASAP 2015: 17-24 - [c11]Heiner Giefers, Raphael Polig, Christoph Hagleitner:
Accelerating arithmetic kernels with coherent attached FPGA coprocessors. DATE 2015: 1072-1077 - 2014
- [j2]Heiner Giefers
An FPGA-Based Reconfigurable Mesh Many-Core. IEEE Trans. Computers 63(12): 2919-2932 (2014) - [c10]Heiner Giefers
Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system. ASAP 2014: 92-99 - [c9]Raphael Polig, Kubilay Atasu
Compiling text analytics queries to FPGAs. FPL 2014: 1-6 - 2013
- [j1]Heiner Giefers, Christian Plessl, Jens Förstner:
Accelerating finite difference time domain simulations with reconfigurable dataflow computers. SIGARCH Comput. Archit. News 41(5): 65-70 (2013) - 2012
- [b1]Heiner Giefers:
Design and programming of reconfigurable mesh based many-cores. University of Paderborn, Logos-Verlag 2012, ISBN 978-3-8325-3165-2, pp. 1-159 - 2010
- [c8]Heiner Giefers, Marco Platzner:
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. ERSA 2010: 251-254 - [c7]Heiner Giefers
A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. FPL 2010: 223-228
2000 – 2009
- 2009
- [c6]Heiner Giefers
Program-driven fine-grained power management for the reconfigurable mesh. FPL 2009: 119-125 - [c5]Heiner Giefers
ARMLang: A language and compiler for programming reconfigurable mesh many-cores. IPDPS 2009: 1-8 - 2008
- [c4]Heiner Giefers
Reconfigurable many-cores with lean interconnect. FPL 2008: 707-708 - [c3]Heiner Giefers
Realizing reconfigurable mesh algorithms on softcore arrays. ICSAMOS 2008: 41-48 - 2007
- [c2]Heiner Giefers
A Many-core Implementation based on the Reconfigurable Mesh Model. FPL 2007: 41-46 - 2006
- [c1]Heiner Giefers
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. SBCCI 2006: 113-118
Coauthor Index
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