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Amara Amara
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2020 – today
- 2022
- [j9]Haikang Diao
, Chen Chen
Real-Time and Cost-Effective Smart Mat System Based on Frequency Channel Selection for Sleep Posture Recognition in IoMT. IEEE Internet Things J. 9(21): 21421-21431 (2022) - [j8]Saeed Akbarzadeh
Predicting Feeding Conditions of Premature Infants Through Non-Nutritive Sucking Skills Using a Sensitized Pacifier. IEEE Trans. Biomed. Eng. 69(7): 2370-2378 (2022) - [c47]Aziza Merzouki, Wessel Valkenburg, Marc Bayala, Maroussia Roelens, Olivia Keiser, Amara Amara:
Improving the quality of anthropometric measures during medical consultations with children aged under five years old in Burkina Faso. BHI 2022: 1-7 - 2021
- [j7]Haikang Diao
Deep Residual Networks for Sleep Posture Recognition With Unobtrusive Miniature Scale Smart Mat System. IEEE Trans. Biomed. Circuits Syst. 15(1): 111-121 (2021) - [c46]Haikang Diao
Unobtrusive Smart Mat System for Sleep Posture Recognition. ISCAS 2021: 1-5 - [c45]Haikang Diao
Edge-Computing System Based on Smart Mat for Sleep Posture Recognition in IoMT. MobiHealth 2021: 85-94 - [c44]Navneet Gupta, Hitesh Shrimali, Adam Makosiej, Andrei Vladimirescu, Amara Amara:
Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC. MWSCAS 2021: 297-300
2010 – 2019
- 2019
- [c43]Sendrine Constant, Balwant Godara, Thierry Agagliate, Nihaalini Kumar, Amara Amara:
Peer Networking and Capacity Building for Child Protection Professionals - Lessons from "ChildHub". ICT4D (1) 2019: 168-180 - [c42]Balwant Godara, Nihaalini Kumar, Frederique Boursin, Gatienne Jobit, Amara Amara, Thierry Agagliate:
ICTs as catalysts in child protection programmes: current landscape in South Asia & a concept to inform future use. ICTD 2019: 55:1-55:6 - 2018
- [d1]Navneet Gupta, Adam Makosiej, Amara Amara, Andrei Vladimirescu, Costin Anghel:
Related references for extended TED submission (uDRAM and uSRAM reference papers). IEEE DataPort, 2018 - 2017
- [c41]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
Tunnel FET based refresh-free-DRAM. DATE 2017: 914-917 - [c40]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell. ESSCIRC 2017: 316-319 - [c39]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
Tunnel FET based ultra-low-leakage compact 2T1C SRAM. ISQED 2017: 71-75 - 2016
- [j6]Khaja Ahmad Shaik, Kiyoo Itoh, Amara Amara:
0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(2): 523-530 (2016) - [j5]Chen Chen, Xue Liu, Adrien Ugon
Symbolic Fusion: A Novel Decision Support Algorithm for Sleep Staging Application. EAI Endorsed Trans. Pervasive Health Technol. 2(8): e4 (2016) - [c38]Chen Chen, Adrien Ugon
Cross entropy-based automatic thresholds setting-up method for sleep staging system. BioCAS 2016: 312-315 - [c37]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. DATE 2016: 361-366 - [c36]Chen Chen, Adrien Ugon
Personalized sleep staging system using evolutionary algorithm and symbolic fusion. EMBC 2016: 2266-2269 - [c35]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell. ESSDERC 2016: 356-359 - [c34]Pablo Perez-Nicoli, Fernando Silveira, Xun Zhang
Uplink wireless transmission overview in bi-directional VLC systems. ICECS 2016: 588-591 - [c33]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
Ultra-compact SRAM design using TFETs for low power low voltage applications. ISCAS 2016: 594-597 - [c32]Jian Song, Sicong Liu, Guangxin Zhou, Bingyan Yu, Wenbo Ding, Fang Yang, Hongming Zhang, Xun Zhang
A cost-effective approach for ubiquitous broadband access based on hybrid PLC-VLC system. ISCAS 2016: 2815-2818 - [c31]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications. ISQED 2016: 107-112 - [c30]Khaja Ahmad Shaik, Kiyoo Itoh, Amara Amara:
0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus. ISQED 2016: 380-385 - [c29]Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana
TFET NDR skewed inverter based sensing method. NANOARCH 2016: 13-14 - 2015
- [c28]Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel:
Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications. ISCAS 2015: 597-600 - [c27]Kiyoo Itoh, Khaja Ahmad Shaik, Amara Amara:
0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell. ISCAS 2015: 2892-2895 - [c26]Andrei Vladimirescu, Costin Anghel, Amara Amara, Navneet Gupta, Adam Makosiej:
Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes. IWASI 2015: 266-270 - [c25]Amara Amara, Navneet Gupta, Khaja Ahmad Shaik, Costin Anghel, Kiyoo Itoh:
Energy efficiency optimization for digital applications in 28nm UTBB FDSOI technology. MIXDES 2015: 23 - 2013
- [c24]Adam Makosiej, Olivier Thomas, Amara Amara, Andrei Vladimirescu:
CMOS SRAM scaling limits under optimum stability constraints. ISCAS 2013: 1460-1463 - 2012
- [c23]Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara:
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization. DATE 2012: 93-98 - [c22]Adam Makosiej, Rutwick Kumar Kashyap, Andrei Vladimirescu, Amara Amara, Costin Anghel:
A 32nm tunnel FET SRAM for ultra low leakage. ISCAS 2012: 2517-2520 - [c21]Islam Seoudi, Jean-Francois Debroux, Marc Laflutte, Alaa Makdissi, Karima Amara, Renzo Dal Molin, Amara Amara:
Default connection in multi-electrode leads for cardiac pacemakers. NEWCAS 2012: 157-160 - [c20]Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller
Bipolar ReRAM Based non-volatile flip-flops for low-power architectures. NEWCAS 2012: 417-420 - 2011
- [c19]Ashutosh Ghildiyal, Balwant Godara, Amara Amara:
Design of an ultra low power MAC for a heterogeneous in-body sensor network. BODYNETS 2011: 60-66 - [c18]Islam Seoudi, Karima Amara, Fabrice Gayral, Renzo Dal Molin, Amara Amara:
Multi-electrode system for pacemaker applications. ICECS 2011: 125-128 - [c17]Ashutosh Ghildiyal, Balwant Godara, Amara Amara:
An Ultra-Low Power MAC Protocol for In-body Medical Implant Networks. MobiHealth 2011: 9-15 - 2010
- [j4]Motoi Ichihashi, Hélène Lhermet, Edith Beigné
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. J. Low Power Electron. 6(1): 201-210 (2010) - [c16]Amara Amara, Bastien Giraud, Olivier Thomas:
An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology. DELTA 2010: 241-244 - [c15]Olivier Thomas, Jean-Philippe Noel, Claire Fenouillet-Béranger, Marie-Anne Jaud, J. Dura, P. Perreau, Frédéric Boeuf, François Andrieu, D. Delprat, F. Boedt, Konstantin Bourdelle
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit. ISCAS 2010: 1703-1706
2000 – 2009
- 2009
- [c14]Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara:
SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch. ISCAS 2009: 3170-3173 - [c13]Motoi Ichihashi, Hélène Lhermet, Edith Beigné
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. PATMOS 2009: 336-346 - 2008
- [c12]Bastien Giraud, Amara Amara:
Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS. DELTA 2008: 201-204 - [c11]Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara:
An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch. ICECS 2008: 554-557 - [c10]Bastien Giraud, Amara Amara:
A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology. ISCAS 2008: 1906-1909 - 2007
- [c9]Bastien Giraud, Amara Amara, Andrei Vladimirescu:
A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. ISCAS 2007: 3022-3025 - 2006
- [j3]Amara Amara, Frédéric Amiel, Thomas Ea:
FPGA vs. ASIC for low power applications. Microelectron. J. 37(8): 669-677 (2006) - [c8]Thomas Ea, Frédéric Amiel, Alicja Michalowska
Contribution of Custom Instructions on SoPC for iris recognition application. ICECS 2006: 455-458 - [c7]Antoine Jalabert, Fabien Clermidy, Amara Amara:
A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire Transistors. ICECS 2006: 1034-1037 - 2005
- [c6]Florence Rossant
Iris identification and robustness evaluation of a wavelet packets based algorithm. ICIP (3) 2005: 257-260 - [c5]Olivier Thomas, Amara Amara:
Ultra low voltage design considerations of SOI SRAM memory cells. ISCAS (4) 2005: 4094-4097 - 2004
- [j2]Jean-François Naviner, Amara Amara:
Systems-on-chip for telecommunications. Ann. des Télécommunications 59(7-8): 755-758 (2004) - [j1]Alexandre Valentian, Olivier Thomas, Andrei Vladimirescu, Amara Amara:
Modeling subthreshold SOI logic for static timing analysis. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 662-669 (2004) - [c4]Erik Rydgren, Thomas Ea, Frédéric Amiel, Florence Rossant
IRIS features extraction using wavelet packets. ICIP 2004: 861-864 - 2003
- [c3]Olivier Thomas, Amara Amara:
An SOI 4 transistors self-refresh ultra-low-voltage memory cell. ISCAS (5) 2003: 401-404 - 2001
- [c2]Arnaud Turier, Lotfi Ben Ammar, Amara Amara:
Static power consumption management in CMOS memories. ISCAS (4) 2001: 506-509
1990 – 1999
- 1996
- [c1]Philippe Royannez, Amara Amara:
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm. Great Lakes Symposium on VLSI 1996: 24-28
Coauthor Index
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last updated on 2024-10-07 22:11 CEST by the dblp team
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