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Vinicius Callegaro
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2010 – 2019
- 2019
- [j5]Felipe S. Marranghello
, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Four-Level Forms for Memristive Material Implication Logic. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1228-1232 (2019) - 2018
- [j4]Augusto Neutzling
A Simple and Effective Heuristic Method for Threshold Logic Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1023-1036 (2018) - 2016
- [j3]Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 692-705 (2016) - 2015
- [j2]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 267-278 (2015) - [c13]Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
SOP based logic synthesis for memristive IMPLY stateful logic. ICCD 2015: 228-235 - [c12]Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD 2015: 680-687 - [c11]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS 2015: 181-184 - 2013
- [c10]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI 2013: 191-196 - [c9]Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Iterative remapping respecting timing constraints. ISVLSI 2013: 236-241 - [c8]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Transistor-level optimization of CMOS complex gates. LASCAS 2013: 1-4 - [c7]Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Read-polarity-once Boolean functions. SBCCI 2013: 1-6 - [c6]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI 2013: 1-6 - 2012
- [c5]Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
KL-cut based digital circuit remapping. NORCHIP 2012: 1-4 - [c4]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI 2012: 1-6 - 2011
- [j1]Renato P. Ribas, Simone Bavaresco, N. Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André Inácio Reis:
Contributions to the evaluation of ensembles of combinational logic gates. Microelectron. J. 42(2): 371-381 (2011) - [c3]Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Efficient method to compute minimum decision chains of Boolean functions. ACM Great Lakes Symposium on VLSI 2011: 419-422 - [c2]Vinícius Dal Bem, Paulo F. Butzen
Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI 2011: 103-108 - 2010
- [c1]Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis:
SwitchCraft: a framework for transistor network design. SBCCI 2010: 49-53
Coauthor Index
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