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Jiayi Zhu 0001
Person information
- affiliation: Waseda University, Graduate School of Information, Production and Systems, Kitakyushu, Japan
Other persons with the same name
- Jiayi Zhu — disambiguation page
- Jiayi Zhu 0002
— East China Normal University, Shanghai Key Lab of Trustworthy Computing, China
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2010 – 2019
- 2017
- [j7]Dajiang Zhou
An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. IEEE J. Solid State Circuits 52(1): 113-126 (2017) - 2016
- [c8]Dajiang Zhou, Shihao Wang
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. ISSCC 2016: 266-268 - 2015
- [j6]Jinjia Zhou
A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2768-2781 (2015) - [c7]Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
An independent bandwidth reduction device for HEVC VLSI video system. ISCAS 2015: 609-612 - 2014
- [j5]Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2488-2497 (2014) - [c6]Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
Fast SAO estimation algorithm and its VLSI architecture. ICIP 2014: 1278-1282 - [c5]Heming Sun
An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder. VCIP 2014: 197-200 - 2013
- [j4]Jiayi Zhu, Dajiang Zhou, Satoshi Goto:
A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2612-2622 (2013) - [c4]Jiayi Zhu, Dajiang Zhou, Gang He, Satoshi Goto:
A combined SAO and de-blocking filter architecture for HEVC video decoder. ICIP 2013: 1967-1971 - 2012
- [c3]Dajiang Zhou, Jinjia Zhou
A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. ISSCC 2012: 224-226 - 2011
- [j3]Dajiang Zhou, Jinjia Zhou
A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. IEEE J. Solid State Circuits 46(4): 777-788 (2011) - 2010
- [j2]Xianmin Chen, Peilin Liu, Dajiang Zhou, Jiayi Zhu, Xingguang Pan, Satoshi Goto:
A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder. IEICE Trans. Electron. 93-C(3): 253-260 (2010)
2000 – 2009
- 2009
- [j1]Dajiang Zhou, Jinjia Zhou
A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3203-3210 (2009) - [c2]Xianmin Chen, Peilin Liu, Jiayi Zhu, Dajiang Zhou, Satoshi Goto:
Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder. ISCAS 2009: 1069-1072 - 2008
- [c1]Jiayi Zhu, Peilin Liu, Dajiang Zhou:
An SDRAM controller optimized for high definition video coding application. ISCAS 2008: 3518-3521
Coauthor Index
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