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Hiroshi Ninomiya
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2020 – today
- 2023
- [j7]Miho Akiyama
, Hiroshi Ninomiya
Method to Achieve High Speed and High Recognition Rate of Goal from Long Distance for CanSat. J. Robotics Mechatronics 35(1): 194-205 (2023) - 2022
- [j6]S. Indrapriyadarsini
Accelerating Symmetric Rank-1 Quasi-Newton Method with Nesterov's Gradient for Training Neural Networks. Algorithms 15(1): 6 (2022) - [c32]S. Indrapriyadarsini, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
On the Practical Robustness of the Nesterov's Accelerated Quasi-Newton Method. AAAI 2022: 12884-12885 - [c31]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
A Stochastic Momentum Accelerated Quasi-Newton Method for Neural Networks (Student Abstract). AAAI 2022: 12973-12974 - [c30]Ryo Yamatomi
Generative Model of Suitable Meme Sentences for Images Using AutoEncoder. PRICAI (1) 2022: 237-248 - 2021
- [i6]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
A modified limited memory Nesterov's accelerated quasi-Newton. CoRR abs/2112.01327 (2021) - 2020
- [c29]S. Indrapriyadarsini
A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton Method. ISCAS 2020: 1 - [i5]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
A Nesterov's Accelerated quasi-Newton method for Global Routing using Deep Reinforcement Learning. CoRR abs/2010.09465 (2020)
2010 – 2019
- 2019
- [c28]Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini
A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. ICMLA 2019: 1874-1879 - [c27]S. Indrapriyadarsini
A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. ECML/PKDD (1) 2019: 743-760 - [c26]Shahrzad Mahboubi
Momentum Acceleration of Quasi-Newton Training for Neural Networks. PRICAI (2) 2019: 268-281 - [i4]S. Indrapriyadarsini
An Adaptive Stochastic Nesterov Accelerated Quasi Newton Method for Training RNNs. CoRR abs/1909.03620 (2019) - [i3]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai:
A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. CoRR abs/1909.03621 (2019) - [i2]Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai:
A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. CoRR abs/1910.07939 (2019) - [i1]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai:
Implementation of a modified Nesterov's Accelerated quasi-Newton Method on Tensorflow. CoRR abs/1910.09158 (2019) - 2018
- [c25]Shahrzad Mahboubi
A Novel quasi-Newton with Momentum Training for Microwave Circuit Models using Neural Networks. ICECS 2018: 629-632 - [c24]S. Indrapriyadarsini
Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on Tensorflow. ICMLA 2018: 1147-1154 - 2017
- [c23]Hiroshi Ninomiya, Yasutomo Kawanishi
Deep Manifold Embedding for 3D Object Pose Estimation. VISIGRAPP (5: VISAPP) 2017: 173-178 - 2016
- [j5]Satoshi Tamura, Hiroshi Ninomiya, Norihide Kitaoka, Shin Osuga, Yurie Iribe, Kazuya Takeda, Satoru Hayamizu:
Investigation of DNN-Based Audio-Visual Speech Recognition. IEICE Trans. Inf. Syst. 99-D(10): 2444-2451 (2016) - 2015
- [c22]Satoshi Tamura, Hiroshi Ninomiya, Norihide Kitaoka, Shin Osuga, Yurie Iribe, Kazuya Takeda, Satoru Hayamizu:
Audio-visual speech recognition using deep bottleneck features and high-performance lipreading. APSIPA 2015: 575-582 - [c21]Hiroshi Ninomiya, Norihide Kitaoka, Satoshi Tamura, Yurie Iribe, Kazuya Takeda:
Integration of deep bottleneck features for audio-visual speech recognition. INTERSPEECH 2015: 563-567 - 2014
- [j4]Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura, Shigeyoshi Watanabe:
Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(2): 675-678 (2014) - [j3]Manabu Kobayashi, Hiroshi Ninomiya, Yasuyuki Miura, Shigeyoshi Watanabe:
Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1051-1058 (2014) - 2013
- [j2]Hiroshi Ninomiya, Manabu Kobayashi, Shigeyoshi Watanabe:
Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(1): 356-359 (2013) - [j1]Manabu Kobayashi, Hiroshi Ninomiya, Shigeyoshi Watanabe:
Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1642-1644 (2013) - [c20]Hiroshi Ninomiya:
Dynamic sample size selection based quasi-Newton training for highly nonlinear function approximation using multilayer neural networks. IJCNN 2013: 1-6 - 2012
- [c19]Manabu Kobayashi, Hiroshi Ninomiya, Toshiyasu Matsushima, Shigeichi Hirasawa:
An error probability estimation of the document classification using Markov model. ISITA 2012: 717-721 - 2011
- [c18]Hiroshi Ninomiya:
Robust Training of Multilayer Neural Networks Using Parameterized Online Quasi-Newton Algorithm. ICMLA (1) 2011: 311-316 - [c17]Hiroshi Ninomiya:
Parameterized online quasi-Newton training for high-nonlinearity function approximation using multilayer neural networks. IJCNN 2011: 2770-2777 - 2010
- [c16]Hiroshi Ninomiya:
An Improved Online quasi-Newton method for robust training and its application to microwave neural network models. IJCNN 2010: 1-8
2000 – 2009
- 2009
- [c15]Hiroshi Ninomiya:
A hybrid global/local optimization technique for robust training of microwave neural network models. IEEE Congress on Evolutionary Computation 2009: 2956-2962 - 2008
- [c14]Hiroshi Ninomiya, Qi-Jun Zhang:
Particle with ability of local search swarm optimization: PALSO for training of feedforward neural networks. IJCNN 2008: 3009-3014 - 2006
- [c13]Hiroshi Ninomiya, Kimihiko Numayama, Hideki Asai:
Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation. IEEE Congress on Evolutionary Computation 2006: 718-724 - 2005
- [c12]Hirokazu Yamagishi, Hiroshi Ninomiya, Hideki Asai:
Three dimensional module packing by simulated annealing. Congress on Evolutionary Computation 2005: 1069-1074 - 2000
- [c11]Teru Yoneyama, Hideki Asai
Design Method of Limit Cycle Generator by Hysteresis Neural Networks. IJCNN (3) 2000: 500-505
1990 – 1999
- 1999
- [c10]Hiroshi Ninomiya, Naoki Kinoshita:
A new learning algorithm without explicit error backpropagation. IJCNN 1999: 1389-1392 - [c9]Teru Yoneyama, Hiroshi Ninomiya, Hideki Asai:
Design method of neural networks for limit cycle generator. IJCNN 1999: 2402-2405 - 1998
- [c8]Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai
Neural network simulator for spatiotemporal pattern analysis. ICECS 1998: 109-112 - 1997
- [c7]Hiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai
Application of neuro-based optimization algorithm to three dimensional cylindric puzzles. ICNN 1997: 1246-1250 - 1996
- [c6]Hideki Asai, Takeshi Nakayama, Hiroshi Ninomiya:
Tiling algorithm with fitting violation function for analog neural array. ICNN 1996: 565-570 - [c5]Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai:
Design and implementation of neuro-based discrete Walsh transform processor. ICNN 1996: 926-931 - 1995
- [c4]Hideki Asai, Katsuaki Onodera, Takeshi Kamio, Hiroshi Ninomiya:
A study of Hopfield neural networks with external noises. ICNN 1995: 1584-1589 - [c3]Hiroshi Ninomiya, Kazumichi Sato, Takeshi Nakayama, Hideki Asai:
Neural network approach to traveling salesman problem based on hierarchical city adjacency. ICNN 1995: 2626-2631 - [c2]Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai:
Convergence of Hopfield Neural Network for Orthogonal Transformation. ISCAS 1995: 493-496 - [c1]Hiroshi Ninomiya, Hideki Asai:
Orthogonalized Steepest Descent Method for Solving Nonlinear Equations. ISCAS 1995: 740-743
Coauthor Index
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