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Manoj Kumar 0005
Person information
- affiliation: Guru Gobind Singh Indraprastha University, New Delhi, India
- affiliation (former): Guru Jambheshwar University of Science & Technology, Hisar, India
Other persons with the same name
- Manoj Kumar — disambiguation page
- Manoj Kumar 0001
(aka: Manoj Kumar Bohra) — Malaviya National Institute of Technology, Jaipur, India
- Manoj Kumar 0002
- Manoj Kumar 0003
- Manoj Kumar 0004
- Manoj Kumar 0006
- Manoj Kumar 0007
- Manoj Kumar 0008
- Manoj Kumar 0009
- Manoj Kumar 0010 — Jawaharlal Nehru University, School of Computer and Systems Sciences, New Delhi, India
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2020 – today
- 2024
- [j11]Vikram Singh, Manoj Kumar
Design of a low power LNA circuit with noise canceling approach in 90 nm CMOS process. Integr. 96: 102163 (2024) - 2023
- [j10]Vivek Jangra
A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology. Integr. 93: 102054 (2023) - 2021
- [j9]Nitin Kumar
Low power CMOS differential ring VCO designs using dual delay stages in 0.13 μm technology for wireless applications. Microelectron. J. 111: 105025 (2021) - [j8]Vikram Singh
A Common-Gate Current-Reuse UWB LNA for Wireless Applications in 90 nm CMOS. Wirel. Pers. Commun. 119(2): 1405-1423 (2021) - [c5]Vivek Jangra
Low Power XNOR based Single Ended VCO Circuit Design with Dynamic Threshold MOS. IC3 2021: 125-131 - 2020
- [j7]Vivek Jangra
Low power active load and IMOS varactor based VCO designs using differential delay stages in 0.18 μm technology. Microelectron. J. 98: 104728 (2020)
2010 – 2019
- 2019
- [j6]Vikram Singh
A 3-14 GHz, Self-Body Biased Common-Gate UWB LNA for Wireless Applications in 90 nm CMOS. J. Circuits Syst. Comput. 28(4): 1950056:1-1950056:21 (2019) - [j5]Nitin Kumar
Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz-6.1 GHz Applications in 0.18 μm CMOS. J. Circuits Syst. Comput. 28(11): 1950182:1-1950182:14 (2019) - 2018
- [j4]Manoj Kumar
Design of Linear Low-Power Voltage-Controlled Oscillator with I-MOS Varactor and Back-Gate Tuning. Circuits Syst. Signal Process. 37(9): 3685-3701 (2018) - [j3]Manoj Kumar
A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control. J. Circuits Syst. Comput. 27(10): 1850160:1-1850160:14 (2018) - [j2]Dinesh Kumar, Manoj Kumar
Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs. Microprocess. Microsystems 60: 107-121 (2018) - 2016
- [c4]Dinesh Kumar, Manoj Kumar
Modified 4-2 compressor using improved multiplexer for low power applications. ICACCI 2016: 236-242 - [c3]Dinesh Kumar, Manoj Kumar
Design of low power two bit magnitude comparator using adiabatic logic. ISPACS 2016: 1-6 - 2012
- [c2]Manoj Kumar
Design of 9-transistor single bit full adder. CCSEIT 2012: 337-340 - [i2]Manoj Kumar, Sandeep Kumar Arya, Sujata Pandey:
Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate. CoRR abs/1201.1966 (2012) - 2011
- [j1]Manoj Kumar
Voltage Controlled Ring Oscillator Design with Novel 3 Transistors XNOR/XOR Gates. Circuits Syst. 2(3): 190-195 (2011) - [c1]Manoj Kumar
Design of CMOS Energy Efficient Single Bit Full Adders. HPAGC 2011: 159-168 - 2010
- [i1]Manoj Kumar, Sandeep Kumar Arya, Sujata Pandey:
Level Shifter Design for Low Power Applications. CoRR abs/1011.0507 (2010)
Coauthor Index
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