default search action
Hao Zhou 0008
Person information
- affiliation: Fudan University, Department of Microelectronics, State Key Laboratory of ASIC and Systems, Shanghai, China
Other persons with the same name
- Hao Zhou — disambiguation page
- Hao Zhou 0001
— University of Science and Technology of China, School of Computer Science and Technology, Hefei, China
- Hao Zhou 0002
- Hao Zhou 0003
- Hao Zhou 0004
- Hao Zhou 0005
- Hao Zhou 0006
- Hao Zhou 0007
- Hao Zhou 0009
- Hao Zhou 0010 — University of Hong Kong, Pokfulam, Hong Kong
- Hao Zhou 0011 — University of Maryland, Center for Automation Research, College Park, MD, USA
- Hao Zhou 0012
- Hao Zhou 0013
- Hao Zhou 0014
- Hao Zhou 0015
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [j6]Yu Qian
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis. ACM Trans. Design Autom. Electr. Syst. 29(2): 25:1-25:33 (2024) - [j5]Enhao Tang
Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 17(4): 58:1-58:33 (2024) - [c25]Yueyin Bai
CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration. DAC 2024: 263:1-263:6 - 2023
- [j4]Kaichuang Shi
An Optimized GIB Routing Architecture with Bent Wires for FPGA. ACM Trans. Reconfigurable Technol. Syst. 16(1): 2:1-2:28 (2023) - [c24]Jide Zhang, Kaixiang Zhu, Kaichuang Shi, Lingli Wang, Hao Zhou:
Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes. ASICON 2023: 1-4 - [c23]Yueyin Bai, Hao Zhou, Keqing Zhao, Jianli Chen, Jun Yu, Kun Wang:
Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks. FCCM 2023: 221 - [c22]Yueyin Bai, Hao Zhou, Keqing Zhao, Manting Zhang, Jianli Chen, Jun Yu, Kun Wang:
LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks. FPL 2023: 283-287 - [c21]Kaichuang Shi, Hao Zhou, Lingli Wang:
VIB: A Versatile Interconnection Block for FPGA Routing Architecture. ICFPT 2023: 79-87 - [c20]Kaichuang Shi, Hao Zhou, Lingli Wang:
Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs. ICFPT 2023: 250-253 - [c19]Zhen Li, Hao Zhou, Lingli Wang, Xuegong Zhou:
AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization. ICFPT 2023: 294-295 - [c18]Yueyin Bai, Hao Zhou, Ruiqi Chen
g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning. ICC 2023: 1706-1711 - [c17]Yueyin Bai, Hao Zhou, Keqing Zhao, Hongji Wang, Jianli Chen, Jun Yu, Kun Wang:
FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks. ICCAD 2023: 1-9 - 2022
- [c16]Fan Ye, Heng Fang, Hao Zhou:
The Research of the Consistency Control Under the Condition of Time-Lag of Isomerism AUV Group Communication. BIC-TA 2022: 507-519 - [c15]Su Zheng, Jiadong Qian, Hao Zhou, Lingli Wang:
GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization. FPL 2022: 282-286 - [c14]Yu Qian
Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration. FPT 2022: 1-6 - 2021
- [j3]Hao Zhou, Hao Min, Ping Luo:
A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability. IEICE Electron. Express 18(8): 20210072 (2021) - [c13]Yuhang Shen, Jiadong Qian, Kaichuang Shi
Two-level MUX Design and Exploration in FPGA Routing Architecture. FPL 2021: 234-241 - [c12]Yuan Dai
APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applications. FPT 2021: 1-8 - [c11]Jiadong Qian, Yuhang Shen, Kaichuang Shi
General routing architecture modelling and exploration for modern FPGAs. FPT 2021: 1-9 - [c10]Kaichuang Shi
A Hexagon-Based Honeycomb Routing Architecture for FPGA. FPT 2021: 1-6 - 2020
- [c9]Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. FPGA 2020: 161-171 - [c8]Kaichuang Shi
GIB: A Novel Unidirectional Interconnection Architecture for FPGA. FPT 2020: 174-181 - [i2]Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong:
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. CoRR abs/2002.12900 (2020) - [i1]Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong:
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. CoRR abs/2003.03043 (2020)
2010 – 2019
- 2019
- [c7]Seyedramin Rasoulinezhad, Hao Zhou, Lingli Wang, Philip H. W. Leong
PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks. FCCM 2019: 35-44 - [c6]Xibo Sun, Hao Zhou, Lingli Wang:
Bent Routing Pattern for FPGA. FPL 2019: 9-16 - [c5]Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. FPT 2019: 339-342 - 2018
- [j2]Hengliang Zhu
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 770-781 (2018) - [j1]Hao Zhou
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1312-1325 (2018) - 2017
- [c4]Kaixuan Zhang, Zhihua Feng, Hao Zhou:
A fast HDL model for full-custom FPGA verification. ASICON 2017: 989-992 - 2015
- [c3]Weizhen Wang, Hao Zhou, Fan Ye, Junyan Ren:
An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. ASICON 2015: 1-4 - 2013
- [c2]Weiru Gu, Hao Zhou, Tao Lin, Zhenyu Wang, Fan Ye, Junyan Ren:
Power efficient SAR ADC with optimized settling technique. MWSCAS 2013: 1156-1159 - 2011
- [c1]Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai:
FPGA interconnect timing library based on the statistical method. ASICON 2011: 393-396
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-26 01:55 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: