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Daniel R. Johnson
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2020 – today
- 2022
- [c15]Sana Damani, Mark Stephenson, Ram Rangan, Daniel R. Johnson, Rishkul Kulkami, Stephen W. Keckler:
GPU Subwarp Interleaving. HPCA 2022: 1184-1197 - 2020
- [c14]Sana Damani, Daniel R. Johnson, Mark Stephenson, Stephen W. Keckler, Eddie Q. Yan, Michael McKeown, Olivier Giroux:
Speculative reconvergence for improved SIMT efficiency. CGO 2020: 121-132
2010 – 2019
- 2017
- [c13]Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally:
Architecting an Energy-Efficient DRAM System for GPUs. HPCA 2017: 73-84 - 2016
- [c12]Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel R. Johnson, Stephen W. Keckler:
A patch memory system for image processing and computer vision. MICRO 2016: 51:1-51:13 - 2015
- [c11]Dong Li, Minsoo Rhu, Daniel R. Johnson, Mike O'Connor, Mattan Erez, Doug Burger, Donald S. Fussell, Stephen W. Redder:
Priority-based cache allocation in throughput processors. HPCA 2015: 89-100 - [c10]Mark Stephenson, Siva Kumar Sastry Hari, Yunsup Lee, Eiman Ebrahimi, Daniel R. Johnson, David W. Nellans, Mike O'Connor, Stephen W. Keckler:
Flexible software profiling of GPU architectures. ISCA 2015: 185-197 - [c9]Timothy G. Rogers, Daniel R. Johnson, Mike O'Connor, Stephen W. Keckler:
A variable warp size architecture. ISCA 2015: 489-501 - 2014
- [c8]Oreste Villa, Daniel R. Johnson, Mike O'Connor, Evgeny Bolotin, David W. Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Stephen W. Keckler, William J. Dally:
Scaling the Power Wall: A Path to Exascale. SC 2014: 830-841 - 2012
- [j4]Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron:
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors. ACM Trans. Comput. Syst. 30(2): 8:1-8:38 (2012) - 2011
- [j3]John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel:
Cohesion: An Adaptive Hybrid Memory Model for Accelerators. IEEE Micro 31(1): 42-55 (2011) - [j2]Daniel R. Johnson, Matthew R. Johnson, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel:
Rigel: A 1, 024-Core Single-Chip Accelerator Architecture. IEEE Micro 31(4): 30-41 (2011) - [c7]Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron:
Energy-efficient mechanisms for managing thread context in throughput processors. ISCA 2011: 235-246 - 2010
- [j1]John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Sanjay J. Patel, Matthew I. Frank:
A Task-Centric Memory Model for Scalable Accelerator Architectures. IEEE Micro 30(1): 29-39 (2010) - [c6]Shobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson:
GoldMine: Automatic assertion generation using data mining and static analysis. DATE 2010: 626-629 - [c5]Stephen M. Kofsky, Daniel R. Johnson, John A. Stratton, Wen-mei W. Hwu, Sanjay J. Patel, Steven S. Lumetta:
Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture. ISCA Workshops 2010: 40-51 - [c4]John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel:
Cohesion: a hybrid memory model for accelerators. ISCA 2010: 429-440
2000 – 2009
- 2009
- [c3]John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel:
A Task-Centric Memory Model for Scalable Accelerator Architectures. PACT 2009: 77-87 - [c2]John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel:
Rigel: an architecture and scalable programming interface for a 1000-core accelerator. ISCA 2009: 140-151 - 2008
- [c1]Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel:
Tradeoffs in designing accelerator architectures for visual computing. MICRO 2008: 164-175
Coauthor Index
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