A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow - Zhiteng Chao; Xindi Zhang; Junying Huang; Zizhen Liu; Yixuan Zhao; Jing Ye; Shaowei Cai; Huawei Li; Xiaowei Li (Integr., 2025)

ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring - Mingjun Wang; Hui Wang; Zizhen Liu; Feng Gu; Jianan Mu; Jiaping Tang; Jun Gao; Huawei Li; Jing Ye; Xiaowei Li (Proceedings of the 30th Asia and South Pacific Design Automation Conference, ASPDAC 2025, Tokyo, Japan, January 20-23, 2025, 2025)

PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System - Yintao He; Haiyu Mao; Christina Giannoula; Mohammad Sadrosadati; Juan Gómez-Luna; Huawei Li; Xiaowei Li; Ying Wang; Onur Mutlu (Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, ASPLOS 2025, Rotterdam, Netherlands, 30 March 2025 - 3 April 2025, 2025)

Frontier-guided Graph Reordering - Xinmiao Zhang; Cheng Liu; Shengwen Liang; Chenwei Xiong; Yu Zhang; Lei Zhang; Huawei Li; Xiaowei Li (Proceedings of the 30th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, PPoPP 2025, Las Vegas, NV, USA, March 1-5, 2025, 2025)

PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System - Yintao He; Haiyu Mao; Christina Giannoula; Mohammad Sadrosadati; Juan Gómez-Luna; Huawei Li; Xiaowei Li; Ying Wang; Onur Mutlu (CoRR, 2025)

Parallel Static Learning Toward Heterogeneous Computing Architectures - Xiaoze Lin; Liyang Lai; Huawei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PDG: A Prefetcher for Dynamic Graph Updating - Xinmiao Zhang; Cheng Liu; Jiacheng Ni; Yuanqing Cheng; Lei Zhang; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference - Lian Liu; Ying Wang; Xiandong Zhao; Weiwei Chen; Huawei Li; Xiaowei Li; Yinhe Han (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating - Mingkai Chen; Cheng Liu; Shengwen Liang; Lei He; Ying Wang; Lei Zhang; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks - Yintao He; Bing Li; Ying Wang; Cheng Liu; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

On Modeling and Detecting Trojans in Instruction Sets - Ying Zhang; Aodi He; Jiaying Li; Ahmed Rezine; Zebo Peng; Erik Larsson; Tao Yang; Jianhui Jiang; Huawei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks - Zizhen Liu; Weiyang He; Chip-Hong Chang; Jing Ye; Huawei Li; Xiaowei Li (IEEE Trans. Inf. Forensics Secur., 2024)

MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing - Haitong Huang; Cheng Liu; Xinghua Xue; Bo Liu; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration - Fuping Li; Ying Wang; Yujie Wang; Mengdi Wang; Yinhe Han; Huawei Li; Xiaowei Li (Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024, 2024)

iEDA: An Open-source infrastructure of EDA - Xingquan Li; Zengrong Huang; Simin Tao; Zhipeng Huang; Chunan Zhuang; Hao Wang; Yifan Li; Yihang Qiu; Guojie Luo; Huawei Li; Haihua Shen; Mingyu Chen; et al. (Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024, 2024)

APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction - Lei Dai; Shengwen Liang; Ying Wang; Huawei Li; Xiaowei Li (Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024, 2024)

A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver - Zhiteng Chao; Xindi Zhang; Junying Huang; Jing Ye; Shaowei Cai; Huawei Li; Xiaowei Li (Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024, 2024)

Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction - Jiaping Tang; Zizhen Liu; Jianan Mu; Feng Gu; Mingjun Wang; Wenxing Li; Jing Ye; Xiaowei Li; Huawei Li (33rd IEEE Asian Test Symposium, ATS 2024, Ahmedabad, India, December 17-20, 2024, 2024)

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption - Jianan Mu; Husheng Han; Shangyi Shi; Jing Ye; Zizhen Liu; Shengwen Liang; Meng Li; Mingzhe Zhang; Song Bian; Xing Hu; Huawei Li; Xiaowei Li (Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024, 2024)

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework - Kaiyan Chang; Kun Wang; Nan Yang; Ying Wang; Dantong Jin; Wenlong Zhu; Zhirong Chen; Cangyuan Li; Hao Yan; Yunhao Zhou; Zhuoliang Zhao; Yuan Cheng; et al. (Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024, 2024)

Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration - Lian Liu; Zhaohui Xu; Yintao He; Ying Wang; Huawei Li; Xiaowei Li; Yinhe Han (Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024, 2024)

Chiplever: Towards Effortless Extension of Chiplet-based System for FHE - Yibo Du; Ying Wang; Bing Li; Fuping Li; Shengwen Liang; Huawei Li; Xiaowei Li; Yinhe Han (Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024, 2024)

SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning - Wenxing Li; Hongqin Lyu; Shengwen Liang; Tiancheng Wang; Huawei Li (Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024, 2024)

GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction - Yibo Du; Shengwen Liang; Ying Wang; Huawei Li; Xiaowei Li; Yinhe Han (Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024, 2024)

Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture - Yintao He; Shixin Zhao; Songyun Qu; Huawei Li; Xiaowei Li; Ying Wang (Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024, 2024)

HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System - Shengwen Liang; Ziming Yuan; Ying Wang; Dawen Xu; Huawei Li; Xiaowei Li (Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024, 2024)

A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256 - Han Yan; Shuai Chen; Junying Huang; Jing Ye; Huawei Li; Xiaowei Li (IEEE European Test Symposium, ETS 2024, The Hague, Netherlands, May 20-24, 2024, 2024)

Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization - Yunkun Liao; Hanyue Lin; Jingya Wu; Wenyan Lu; Huawei Li; Xiaowei Li; Guihai Yan (Euro-Par 2024: Parallel Processing - 30th European Conference on Parallel and Distributed Processing, Madrid, Spain, August 26-30, 2024, Proceedings, Part II, 2024)

DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism - Feng Gu; Mingjun Wang; Jianan Mu; Zizhen Liu; Jiaping Tang; Hui Wang; Yonghao Wang; Jing Ye; Huawei Li; Xiaowei Li (Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2024, Newark Liberty International Airport Marriott, NJ, USA, October 27-31, 2024, 2024)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation - Kaiyan Chang; Zhirong Chen; Yunhao Zhou; Wenlong Zhu; Kun Wang; Haobo Xu; Cangyuan Li; Mengdi Wang; Shengwen Liang; Huawei Li; Yinhe Han; Ying Wang (Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2024, Newark Liberty International Airport Marriott, NJ, USA, October 27-31, 2024, 2024)

A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification - Zhiteng Chao; Qinluan Dai; Jiale Li; Zizhen Liu; Wenxing Li; Hongqin Lyu; Jing Ye; Huawei Li; Xiaowei Li (IEEE International Test Conference in Asia, ITC-Asia 2024, Changsha, China, August 18-20, 2024, 2024)

Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262 - Mingjun Wang; Hui Wang; Jianan Mu; Zizhen Liu; Jun Gao; Jing Ye; Huawei Li; Xiaowei Li (IEEE International Test Conference in Asia, ITC-Asia 2024, Changsha, China, August 18-20, 2024, 2024)

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework - Kaiyan Chang; Kun Wang; Nan Yang; Ying Wang; Dantong Jin; Wenlong Zhu; Zhirong Chen; Cangyuan Li; Hao Yan; Yunhao Zhou; Zhuoliang Zhao; Yuan Cheng; et al. (CoRR, 2024)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation - Kaiyan Chang; Zhirong Chen; Yunhao Zhou; Wenlong Zhu; Kun Wang; Haobo Xu; Cangyuan Li; Mengdi Wang; Shengwen Liang; Huawei Li; Yinhe Han; Ying Wang (CoRR, 2024)

ApproxPilot: A GNN-based Accelerator Approximation Framework - Qing Zhang; Cheng Liu; Siting Liu; Yajuan Hui; Huawei Li; Xiaowei Li (CoRR, 2024)

SigDLA: A Deep Learning Accelerator Extension for Signal Processing - Fangfa Fu; Wenyu Zhang; Zesong Jiang; Zhiyu Zhu; Guoyu Li; Bing Yang; Cheng Liu; Liyi Xiao; Jinxiang Wang; Huawei Li; Xiaowei Li (CoRR, 2024)

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation - Xinmiao Zhang; Zheng Feng; Shengwen Liang; Xinyu Chen; Cheng Liu; Huawei Li; Xiaowei Li (CoRR, 2024)

IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA - Zesong Jiang; Qing Zhang; Cheng Liu; Huawei Li; Xiaowei Li (CoRR, 2024)

OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis - Liwei Ni; Rui Wang; Miao Liu; Xingyu Meng; Xiaoze Lin; Junfeng Liu; Guojie Luo; Zhufei Chu; Weikang Qian; Xiaoyan Yang; Biwei Xie; Xingquan Li; et al. (CoRR, 2024)

Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network - Liwei Ni; Xinquan Li; Biwei Xie; Huawei Li (CoRR, 2024)

Chosen ciphertext correlation power analysis on Kyber - Yipei Yang; Zongyue Wang; Jing Ye; Junfeng Fan; Shuai Chen; Huawei Li; Xiaowei Li; Yuan Cao (Integr., 2023)

On-Line Fault Protection for ReRAM-Based Neural Networks - Wen Li; Ying Wang; Cheng Liu; Yintao He; Lian Liu; Huawei Li; Xiaowei Li (IEEE Trans. Computers, 2023)

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation - Jianan Mu; Yi Ren; Wen Wang; Yizhong Hu; Shuai Chen; Chip-Hong Chang; Junfeng Fan; Jing Ye; Yuan Cao; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Statistical Modeling of Soft Error Influence on Neural Networks - Haitong Huang; Xinghua Xue; Cheng Liu; Ying Wang; Tao Luo; Long Cheng; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning - Zizhen Liu; Si Chen; Jing Ye; Junfeng Fan; Huawei Li; Xiaowei Li (J. Supercomput., 2023)

Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses - Cheng Chu; Cheng Liu; Dawen Xu; Ying Wang; Tao Luo; Huawei Li; Xiaowei Li (ACM Trans. Design Autom. Electr. Syst., 2023)

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance - Xinghua Xue; Cheng Liu; Bo Liu; Haitong Huang; Ying Wang; Tao Luo; Lei Zhang; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Soft Error Reliability Analysis of Vision Transformers - Xinghua Xue; Cheng Liu; Ying Wang; Bing Yang; Tao Luo; Lei Zhang; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT - Zhiteng Chao; Senlin Wang; Pengyu Tian; Shuwen Yuan; Huawei Li; Jing Ye; Xiaowei Li (32nd IEEE Asian Test Symposium, ATS 2023, Beijing, China, October 14-17, 2023, 2023)

Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning - Wenxing Li; Hongqin Lyu; Shengwen Liang; Tiancheng Wang; Pengyu Tian; Huawei Li (32nd IEEE Asian Test Symposium, ATS 2023, Beijing, China, October 14-17, 2023, 2023)

Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors - Wen Li; Ying Wang; Kaiwei Zou; Huawei Li; Xiaowei Li (32nd IEEE Asian Test Symposium, ATS 2023, Beijing, China, October 14-17, 2023, 2023)

Message from the Chairs - Huawei Li; Jing Ye; Wei Hu; Jiliang Zhang (32nd IEEE Asian Test Symposium, ATS 2023, Beijing, China, October 14-17, 2023, 2023)

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design - Jianan Mu; Huajie Tan; Shuai Chen; Min Cai; Jing Ye; Huawei Li; Xiaowei Li (32nd IEEE Asian Test Symposium, ATS 2023, Beijing, China, October 14-17, 2023, 2023)

A Template Attack on Reduction Without Reference Device on Kyber - Yipei Yang; Junying Huang; Zongyue Wang; Jing Ye; Zihao Sun; Junfeng Fan; Shuai Chen; Huawei Li; Xiaowei Li; Yuan Cao (32nd IEEE Asian Test Symposium, ATS 2023, Beijing, China, October 14-17, 2023, 2023)

APPEND: Rethinking ASIP Synthesis in the Era of AI - Cangyuan Li; Ying Wang; Huawei Li; Yinhe Han (60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, 2023)

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array - Jianan Mu; Huajie Tan; Jiawen Wu; Haotian Lu; Chip-Hong Chang; Shuai Chen; Shengwen Liang; Jing Ye; Huawei Li; Xiaowei Li (Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, 2023)

Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions - Jiaxi Zhang; Shenggen Zheng; Liwei Ni; Huawei Li; Guojie Luo (Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, 2023)

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants - Chaofang Ma; Jianan Mu; Jing Ye; Shuai Chen; Yuan Cao; Huawei Li; Xiaowei Li (IEEE European Test Symposium, ETS 2023, Venezia, Italy, May 22-26, 2023, 2023)

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs - Erjing Luo; Haitong Huang; Cheng Liu; Guoyu Li; Bing Yang; Ying Wang; Huawei Li; Xiaowei Li (IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023, 2023)

Fast Exact NPN Classification with Influence-Aided Canonical Form - Yonghe Zhang; Liwei Ni; Jiaxi Zhang; Guojie Luo; Huawei Li; Shenggen Zheng (IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023, 2023)

PANG: A Pattern-Aware GCN Accelerator for Universal Graphs - Yibo Du; Ying Wang; Shengwen Liang; Huawei Li; Xiaowei Li; Yinhe Han (41st IEEE International Conference on Computer Design, ICCD 2023, Washington, DC, USA, November 6-8, 2023, 2023)

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning - Liwei Ni; Zonglin Yang; Jiaxi Zhang; Junfeng Liu; Huawei Li; Biwei Xie; Xinquan Li (41st IEEE International Conference on Computer Design, ICCD 2023, Washington, DC, USA, November 6-8, 2023, 2023)

Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators - Kaiwei Zou; Songyun Qu; Wen Li; Ying Wang; Huawei Li; Yongpan Liu (29th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2023, Ocean Flower Island, China, December 17-21, 2023, 2023)

Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions - Jiaxi Zhang; Shenggen Zheng; Liwei Ni; Huawei Li; Guojie Luo (CoRR, 2023)

Reliability Analysis of Vision Transformers - Xinghua Xue; Cheng Liu; Ying Wang; Bing Yang; Tao Luo; Lei Zhang; Huawei Li; Xiaowei Li (CoRR, 2023)

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers - Xinghua Xue; Cheng Liu; Haitong Huang; Ying Wang; Bing Yang; Tao Luo; Lei Zhang; Huawei Li; Xiaowei Li (CoRR, 2023)

ChipGPT: How far are we from natural language hardware design - Kaiyan Chang; Ying Wang; Haimeng Ren; Mengdi Wang; Shengwen Liang; Yinhe Han; Huawei Li; Xiaowei Li (CoRR, 2023)

MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing - Haitong Huang; Cheng Liu; Xinghua Xue; Ying Wang; Huawei Li; Xiaowei Li (CoRR, 2023)

iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library - Xingquan Li; Simin Tao; Zengrong Huang; Shijian Chen; Zhisheng Zeng; Liwei Ni; Zhipeng Huang; Chunan Zhuang; Hongxi Wu; Weiguo Li; Xueyan Zhao; He Liu; et al. (CoRR, 2023)

Exploring Winograd Convolution for Cost-effective Neural Network Fault Tolerance - Xinghua Xue; Cheng Liu; Bo Liu; Haitong Huang; Ying Wang; Tao Luo; Lei Zhang; Huawei Li; Xiaowei Li (CoRR, 2023)

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs - Erjing Luo; Haitong Huang; Cheng Liu; Guoyu Li; Bing Yang; Ying Wang; Huawei Li; Xiaowei Li (CoRR, 2023)

Fast Exact NPN Classification with Influence-aided Canonical Form - Yonghe Zhang; Liwei Ni; Jiaxi Zhang; Guojie Luo; Huawei Li; Shenggen Zheng (CoRR, 2023)

SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks - Zizhen Liu; Weiyang He; Chip-Hong Chang; Jing Ye; Huawei Li; Xiaowei Li (CoRR, 2023)

Cross-Layer Optimization for Fault-Tolerant Deep Learning - Qing Zhang; Cheng Liu; Bo Liu; Haitong Huang; Ying Wang; Huawei Li; Xiaowei Li (CoRR, 2023)

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning - Liwei Ni; Zonglin Yang; Jiaxi Zhang; Junfeng Liu; Huawei Li; Biwei Xie; Xinquan Li (CoRR, 2023)

MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA - Liwei Ni; Zonglin Yang; Jiaxi Zhang; Changhong Feng; Jianhua Liu; Guojie Luo; Huawei Li; Biwei Xie; Xingquan Li (CoRR, 2023)

Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval - Shengwen Liang; Ying Wang; Huawei Li; Xiaowei Li (CCF Trans. High Perform. Comput., 2022)

CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures - Kaiwei Zou; Ying Wang; Long Cheng; Songyun Qu; Huawei Li; Xiaowei Li (IEEE Trans. Computers, 2022)

A Fast Precision Tuning Solution for Always-On DNN Accelerators - Ying Wang; Yintao He; Long Cheng; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing - Yintao He; Ying Wang; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis - Yongchen Wang; Ying Wang; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning - Cheng Liu; Cheng Chu; Dawen Xu; Ying Wang; Qianlong Wang; Huawei Li; Xiaowei Li; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding - Aijiao Cui; Zhen Weng; Hui Zhang; Gang Qu; Huawei Li (IEEE Trans. Emerg. Top. Comput., 2022)

Taming Process Variations in CNFET for Efficient Last-Level Cache Design - Dawen Xu; Zhuangyu Feng; Cheng Liu; Li Li; Ying Wang; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2022)

BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature - Ying Zhang; Yi Ding; Zebo Peng; Huawei Li; Masahiro Fujita; Jianhui Jiang (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber - Jianan Mu; Yixuan Zhao; Zongyue Wang; Jing Ye; Junfeng Fan; Shuai Chen; Huawei Li; Xiaowei Li; Yuan Cao (27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, 2022)

A Hardware Trojan Trigger Localization Method in RTL based on Control Flow Features - Hao Huang; Haihua Shen; Shan Li; Huawei Li (IEEE 31st Asian Test Symposium, ATS 2022, Taichung City, Taiwan, November 21-24, 2022, 2022)

InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs - Yintao He; Songyun Qu; Ying Wang; Bing Li; Huawei Li; Xiaowei Li (DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, 2022)

VStore: in-storage graph based vector search accelerator - Shengwen Liang; Ying Wang; Ziming Yuan; Cheng Liu; Huawei Li; Xiaowei Li (DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, 2022)

NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network - Fuping Li; Ying Wang; Cheng Liu; Huawei Li; Xiaowei Li (2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, 2022)

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration - Fuping Li; Ying Wang; Yuanqing Cheng; Yujie Wang; Yinhe Han; Huawei Li; Xiaowei Li (Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022, 2022)

Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance - Lei Dai; Ying Wang; Cheng Liu; Fuping Li; Huawei Li; Xiaowei Li (IEEE 40th International Conference on Computer Design, ICCD 2022, Olympic Valley, CA, USA, October 23-26, 2022, 2022)

Exploring the high-throughput and low-delay hardware design of SM4 on FPGA - Yixiao Chen; Jinfeng Song; Shuai Chen; Yuan Cao; Jing Ye; Huawei Li; Xiaowei Li; Xin Lou; Enyi Yao (19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022, 2022)

SASH: Efficient secure aggregation based on SHPRG for federated learning - Zizhen Liu; Si Chen; Jing Ye; Junfeng Fan; Huawei Li; Xiaowei Li (Uncertainty in Artificial Intelligence, Proceedings of the Thirty-Eighth Conference on Uncertainty in Artificial Intelligence, UAI 2022, 1-5 August 2022, Eindhoven, The Netherlands, 2022)

Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective - Cheng Liu; Zhen Gao; Siting Liu; Xuefei Ning; Huawei Li; Xiaowei Li (40th IEEE VLSI Test Symposium, VTS 2022, San Diego, CA, USA, April 25-27, 2022, 2022)

Fault-Tolerant Deep Learning: A Hierarchical Perspective - Cheng Liu; Zhen Gao; Siting Liu; Xuefei Ning; Huawei Li; Xiaowei Li (CoRR, 2022)

DHSA: Efficient Doubly Homomorphic Secure Aggregation for Cross-silo Federated Learning - Zizhen Liu; Si Chen; Jing Ye; Junfeng Fan; Huawei Li; Xiaowei Li (CoRR, 2022)

Statistical Modeling of Soft Error Influence on Neural Networks - Haitong Huang; Xinghua Xue; Cheng Liu; Ying Wang; Tao Luo; Long Cheng; Huawei Li; Xiaowei Li (CoRR, 2022)

Editorial for the special issue on reliability and power efficiency for HPC - Jifeng He; Chenggang Wu; Huawei Li; Yang Guo; Tao Li (CCF Trans. High Perform. Comput., 2021)

To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices - Yibin Tang; Ying Wang; Huawei Li; Xiaowei Li (CCF Trans. High Perform. Comput., 2021)

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks - Shengwen Liang; Ying Wang; Cheng Liu; Lei He; Huawei Li; Dawen Xu; Xiaowei Li (IEEE Trans. Computers, 2021)

An Edge 3D CNN Accelerator for Low-Power Activity Recognition - Ying Wang; Yongchen Wang; Cong Shi; Long Cheng; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System - Dawen Xu; Ziyang Zhu; Cheng Liu; Ying Wang; Shuang Zhao; Lei Zhang; Huaguo Liang; Huawei Li; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors - Dawen Xu; Meng He; Cheng Liu; Ying Wang; Long Cheng; Huawei Li; Xiaowei Li; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

SeGa: A Trojan Detection Method Combined With Gate Semantics - Yunying Ye; Shan Li; Haihua Shen; Huawei Li; Xiaowei Li (30th IEEE Asian Test Symposium, ATS 2021, Matsuyama, Ehime, Japan, November 22-25, 2021, 2021)

GCiM: A Near-Data Processing Accelerator for Graph Construction - Lei He; Cheng Liu; Ying Wang; Shengwen Liang; Huawei Li; Xiaowei Li (58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, 2021)

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning - Yintao He; Ying Wang; Cheng Liu; Huawei Li; Xiaowei Li (58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, 2021)

PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams - Yongchen Wang; Ying Wang; Huawei Li; Xiaowei Li (58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, 2021)

Scalable Parallel Static Learning - Xiaoze Lin; Liyang Lai; Huawei Li (IEEE International Test Conference in Asia, ITC-Asia 2021, Shanghai, China, August 18-20, 2021, 2021)

GLIST: Towards In-Storage Graph Learning - Cangyuan Li; Ying Wang; Cheng Liu; Shengwen Liang; Huawei Li; Xiaowei Li (Proceedings of the 2021 USENIX Annual Technical Conference, USENIX ATC 2021, July 14-16, 2021, 2021)

Special Session - Test for AI Chips: from DFT to On-line Testing - Huawei Li; Xiaowei Li; Yu Huang; Ying Wang; Gary Guo (39th IEEE VLSI Test Symposium, VTS 2021, San Diego, CA, USA, April 25-28, 2021, 2021)

HyCA: A Hybrid Computing Architecture for Fault Tolerant Deep Learning - Dawen Xu; Qianlong Wang; Cheng Liu; Cheng Chu; Ying Wang; Huawei Li; Xiaowei Li; Kwang-Ting Cheng (CoRR, 2021)

Energy-Efficient Accelerator Design for Deformable Convolution Networks - Dawen Xu; Cheng Chu; Cheng Liu; Ying Wang; Huawei Li; Xiaowei Li; Kwang-Ting Cheng (CoRR, 2021)

R2F: A Remote Retraining Framework for AIoT Processors with Computing Errors - Dawen Xu; Meng He; Cheng Liu; Ying Wang; Long Cheng; Huawei Li; Xiaowei Li; Kwang-Ting Cheng (CoRR, 2021)

Taming Process Variations in CNFET for Efficient Last Level Cache Design - Dawen Xu; Zhuangyu Feng; Cheng Liu; Li Li; Ying Wang; Yuanqing Cheng; Huawei Li; Xiaowei Li (CoRR, 2021)

Efficient Secure Aggregation Based on SHPRG For Federated Learning - Zizhen Liu; Si Chen; Jing Ye; Junfeng Fan; Huawei Li; Xiaowei Li (CoRR, 2021)

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection - Qingli Guo; Jing Ye; Yu Hu; Guohe Zhang; Xiaowei Li; Huawei Li (IEEE Access, 2020)

Evaluating and Constraining Hardware Assertions with Absent Scenarios - Huina Chao; Huawei Li; Xiaoyu Song; Tiancheng Wang; Xiaowei Li (J. Comput. Sci. Technol., 2020)

GPGPU-Based ATPG System: Myth or Reality? - Liyang Lai; Kun-Han Tsai; Huawei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors - Ying Zhang; Krishnendu Chakrabarty; Zebo Peng; Ahmed Rezine; Huawei Li; Petru Eles; Jianhui Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Architecting Effectual Computation for Machine Learning Accelerators - Hang Lu; Mingzhe Zhang; Yinhe Han; Qi Wang; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash - Aijiao Cui; Mengyang Li; Gang Qu; Huawei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System - Dawen Xu; Ziyang Zhu; Cheng Liu; Ying Wang; Huawei Li; Lei Zhang; Kwang-Ting Cheng (31st IEEE International Conference on Application-specific Systems, Architectures and Processors , ASAP 2020, Manchester, United Kingdom, July 6-8, 2020, 2020)

Survey: Hardware Trojan Detection for Netlist - Yipei Yang; Jing Ye; Yuan Cao; Jiliang Zhang; Xiaowei Li; Huawei Li; Yu Hu (29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020, 2020)

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER - Yixuan Zhao; Zhiteng Chao; Jing Ye; Wen Wang; Yuan Cao; Shuai Chen; Xiaowei Li; Huawei Li (29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020, 2020)

Towards State-Aware Computation in ReRAM Neural Networks - Yintao He; Ying Wang; Xiandong Zhao; Huawei Li; Xiaowei Li (57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, 2020)

An Efficient Deep Learning Accelerator for Compressed Video Analysis - Yongchen Wang; Ying Wang; Huawei Li; Yinhe Han; Xiaowei Li (57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, 2020)

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding - Dawen Xu; Kexin Chu; Cheng Liu; Ying Wang; Lei Zhang; Huawei Li (2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, 2020)

HIT: A Hidden Instruction Trojan Model for Processors - Jiaqi Zhang; Ying Zhang; Huawei Li; Jianhui Jiang (2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, 2020)

Multi-task Scheduling for PIM-based Heterogeneous Computing System - Dawen Xu; Cheng Chu; Cheng Liu; Ying Wang; Xianzhong Zhou; Lei Zhang; Huaguo Liang; Huawei Li (GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020, 2020)

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs - Qingli Guo; Jing Ye; Jiliang Zhang; Yu Hu; Xiaowei Li; Huawei Li (GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020, 2020)

A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning - Ying Wang; Mengdi Wang; Bing Li; Huawei Li; Xiaowei Li (IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, 2020)

DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators - Shengwen Liang; Cheng Liu; Ying Wang; Huawei Li; Xiaowei Li (IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, 2020)

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis - Rajendra Bishnoi; Lizhou Wu; Moritz Fieback; Christopher Münch; Sarath Mohanachandran Nair; Mehdi Baradaran Tahoori; Ying Wang; Huawei Li; Said Hamdioui (38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020, 2020)

Sequence Triggered Hardware Trojan in Neural Network Accelerator - Zizhen Liu; Jing Ye; Xing Hu; Huawei Li; Xiaowei Li; Yu Hu (38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020, 2020)

A New Secure Scan Design with PUF-based Key for Authentication - Qidong Wang; Aijiao Cui; Gang Qu; Huawei Li (38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020, 2020)

Scan Chain Based Attacks and Countermeasures: A Survey - Xiaowei Li; Wenjie Li; Jing Ye; Huawei Li; Yu Hu (IEEE Access, 2019)

MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems - Yibin Tang; Ying Wang; Huawei Li; Xiaowei Li (ACM J. Emerg. Technol. Comput. Syst., 2019)

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug - Yun Cheng; Huawei Li; Ying Wang; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A QoS-QoR Aware CNN Accelerator Design Approach - Ying Wang; Huawei Li; Long Cheng; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Resilient Neural Network Training for Accelerators with Computing Errors - Dawen Xu; KouZi Xing; Cheng Liu; Ying Wang; Yulin Dai; Long Cheng; Huawei Li; Lei Zhang (30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019, 2019)

Exploring emerging CNFET for efficient last level cache design - Dawen Xu; Li Li; Ying Wang; Cheng Liu; Huawei Li (Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019, 2019)

P\(^3\)M: a PIM-based neural network model protection scheme for deep learning accelerator - Wen Li; Ying Wang; Huawei Li; Xiaowei Li (Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019, 2019)

GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network - Renjie Lu; Haihua Shen; Yu Su; Huawei Li; Xiaowei Li (28th IEEE Asian Test Symposium, ATS 2019, Kolkata, India, December 10-13, 2019, 2019)

A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs - Ying Wang; Shengwen Liang; Huawei Li; Xiaowei Li (Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, 2019)

Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis - Yongchen Wang; Ying Wang; Huawei Li; Cong Shi; Xiaowei Li (Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, 2019)

Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture - Kaiwei Zou; Ying Wang; Huawei Li; Xiaowei Li (Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, 2019)

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing - Shengwen Liang; Ying Wang; Cheng Liu; Huawei Li; Xiaowei Li (29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, September 8-12, 2019, 2019)

An Agile Precision-Tunable CNN Accelerator based on ReRAM - Yintao He; Ying Wang; Yongchen Wang; Huawei Li; Xiaowei Li (Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019, 2019)

RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime - Wen Li; Ying Wang; Huawei Li; Xiaowei Li (37th IEEE International Conference on Computer Design, ICCD 2019, Abu Dhabi, United Arab Emirates, November 17-20, 2019, 2019)

Fuzzy Association Rule Mining Algorithm Based on Load Classifier - Jing Chen; Hui Zheng; Peng Li; Zhenjiang Zhang; Huawei Li; Wei Liu (Data Science - 6th International Conference, ICDS 2019, Ningbo, China, May 15-20, 2019, Revised Selected Papers, 2019)

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack - Kuozhong Zhang; Junying Huang; Jing Ye; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li; Xiaowei Li; Zhimin Zhang (25th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, Rhodes, Greece, July 1-3, 2019, 2019)

China Test Conference (CTC) - Extending the Global Test Forum to China - Huawei Li; Xiaowei Li; Yinhe Han (IEEE International Test Conference, ITC 2019, Washington, DC, USA, November 9-15, 2019, 2019)

Implementation of Parametric Hardware Trojan in FPGA - Yipei Yang; Jing Ye; Xiaowei Li; Yinhe Han; Huawei Li; Yu Hu (IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019, 2019)

Instruction Vulnerability Test and Code Optimization Against DVFS Attack - Junying Huang; Jing Ye; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li; Xiaowei Li; Zhimin Zhang (IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019, 2019)

Squeezing the Last MHz for CNN Acceleration on FPGAs - Li Li; Dawen Xu; Kouzi Xing; Cheng Liu; Ying Wang; Huawei Li; Xiaowei Li (IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019, 2019)

A Memristor-based Scan Hold Flip-Flop - Aijiao Cui; Zhenxing Chang; Ziming Wang; Gang Qu; Huawei Li (2019 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2019, Hangzhou, China, August 18-21, 2019, 2019)

Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval - Shengwen Liang; Ying Wang; Youyou Lu; Zhe Yang; Huawei Li; Xiaowei Li (Proceedings of the 2019 USENIX Annual Technical Conference, USENIX ATC 2019, Renton, WA, USA, July 10-12, 2019, 2019)

A Secure and Low-overhead Active IC Metering Scheme - Aijiao Cui; Yan Yang; Gang Qu; Huawei Li (37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019, 2019)

Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems - Wen Li; Ying Wang; Huawei Li; Xiaowei Li (37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019, 2019)

HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection - Renjie Lu; Haihua Shen; Feng Zhang; Huawei Li; Wei Zhao; Xiaowei Li (CoRR, 2019)

CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency - Faqiang Sun; Guihai Yan; Xin He; Huawei Li; Yinhe Han (J. Comput. Sci. Technol., 2018)

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors - Ying Wang; Huawei Li; Yinhe Han; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators - Ying Wang; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug - Yun Cheng; Huawei Li; Ying Wang; Haihua Shen; Bo Liu; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection - Haihua Shen; Huazhe Tan; Huawei Li; Feng Zhang; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Bias PUF based Secure Scan Chain Design - Wenjie Li; Jing Ye; Xiaowei Li; Huawei Li; Yu Hu (Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2018, Hong Kong, China, December 17-18, 2018, 2018)

XORiM: A case of in-memory bit-comparator implementation and its performance implications - Kaiwei Zou; Ying Wang; Huawei Li; Xiaowei Li (23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, 2018)

A low-overhead PUF based on parallel scan design - Wenxuan Wang; Aijiao Cui; Gang Qu; Huawei Li (23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, 2018)

Hardware Trojan Detection Based on Signal Correlation - Wei Zhao; Haihua Shen; Huawei Li; Xiaowei Li (27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018, 2018)

A New Scheme to Extract PUF Information by Scan Chain - Aijiao Cui; Wei Zhou; Gang Qu; Huawei Li (27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018, 2018)

A retrospective evaluation of energy-efficient object detection solutions on embedded devices - Ying Wang; Zhenyu Quan; Jiajun Li; Yinhe Han; Huawei Li; Xiaowei Li (2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, 2018)

FCN-engine: accelerating deconvolutional layers in classic CNN processors - Dawen Xu; Kaijie Tu; Ying Wang; Cheng Liu; Bingsheng He; Huawei Li (Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018)

Lightweight Timing Channel Protection for Shared DRAM Controller - Ying Wang; Wen Li; Huawei Li; Xiaowei Li (IEEE International Test Conference, ITC 2018, Phoenix, AZ, USA, October 29 - Nov. 1, 2018, 2018)

Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors - Ying Wang; Wen Li; Huawei Li; Xiaowei Li (IEEE International Test Conference in Asia, ITC-Asia 2018, Harbin, China, August 15-17, 2018, 2018)

Small Trojan Testing Using Bounded Model Checking - Ying Zhang; Lu Yu; Huawei Li; Jianhui Jiang (IEEE International Test Conference in Asia, ITC-Asia 2018, Harbin, China, August 15-17, 2018, 2018)

Innovative practices on challenges, opportunities, and solutions to hardware security - Sohrab Aftabjahani; Jason Oberg; Michael Chen; Huawei Li (36th IEEE VLSI Test Symposium, VTS 2018, San Francisco, CA, USA, April 22-25, 2018, 2018)

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF - Jing Ye; Qingli Guo; Yu Hu; Huawei Li; Xiaowei Li (36th IEEE VLSI Test Symposium, VTS 2018, San Francisco, CA, USA, April 22-25, 2018, 2018)

Why current secure scan designs fail and how to fix them? - Aijiao Cui; Yanhui Luo; Huawei Li; Gang Qu (Integr., 2017)

Retention-Aware DRAM Assembly and Repair for Future FGR Memories - Ying Wang; Yinhe Han; Cheng Wang; Huawei Li; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Editorial - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator - Lili Song; Ying Wang; Yinhe Han; Huawei Li; Yuanqing Cheng; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips - Ying Wang; Jiachao Deng; Yuntan Fang; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2017)

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory - Yibin Tang; Ying Wang; Huawei Li; Xiaowei Li (22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017)

A New Active IC Metering Technique Based on Locking Scan Cells - Aijiao Cui; Xuesen Qian; Gang Qu; Huawei Li (26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017, 2017)

How to Secure Scan Design Against Scan-Based Side-Channel Attacks? - Wei Zhou; Aijiao Cui; Huawei Li; Gang Qu (26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017, 2017)

Test and Reliability of Emerging Non-volatile Memories - Said Hamdioui; Peyman Pouyan; Huawei Li; Ying Wang; Arijit Raychowdhury; Insik Yoon (26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017, 2017)

On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios - Huina Chao; Huawei Li; Xiaoyu Song; Tiancheng Wang; Xiaowei Li (26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017, 2017)

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems - Dawen Xu; Yi Liao; Ying Wang; Huawei Li; Xiaowei Li (Proceedings of the Computing Frontiers Conference, CF'17, Siena, Italy, May 15-17, 2017, 2017)

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR - Ying Wang; Huawei Li; Xiaowei Li (Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017, 2017)

Software-based online self-testing of network-on-chip using bounded model checking - Ying Zhang; Krishnendu Chakrabarty; Huawei Li; Jianhui Jiang (IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017, 2017)

Flip-flop clustering based trace signal selection for post-silicon debug - Yun Cheng; Huawei Li; Ying Wang; Yingke Gao; Bo Liu; Xiaowei Li (35th IEEE VLSI Test Symposium, VTS 2017, Las Vegas, NV, USA, April 9-12, 2017, 2017)

Innovative practices session 10C formal verification practices in industry - Huawei Li; Xiaowei Li (35th IEEE VLSI Test Symposium, VTS 2017, Las Vegas, NV, USA, April 9-12, 2017, 2017)

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs - Jun Zhou; Huawei Li; Tiancheng Wang; Xiaowei Li (Integr., 2016)

CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition - Guihai Yan; Faqiang Sun; Huawei Li; Xiaowei Li (IEEE Trans. Computers, 2016)

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification - Jian Wang; Huawei Li; Tao Lv; Tiancheng Wang; Xiaowei Li; Sandip Kundu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving - Yanhong Zhou; Tiancheng Wang; Huawei Li; Tao Lv; Xiaowei Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands - Song Jin; Songwei Pei; Yinhe Han; Huawei Li (ACM Trans. Design Autom. Electr. Syst., 2016)

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache - Ying Wang; Yinhe Han; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM - Ying Wang; Yinhe Han; Huawei Li; Lei Zhang; Yuanqing Cheng; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools - Yingxin Qiu; Huawei Li; Tiancheng Wang; Bo Liu; Yingke Gao; Xiaowei Li (25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016)

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors - Ying Wang; Yinhe Han; Jun Zhou; Huawei Li; Xiaowei Li (Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016, 2016)

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family - Ying Wang; Jie Xu; Yinhe Han; Huawei Li; Xiaowei Li (Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016, 2016)

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage - Ying Wang; Huawei Li; Xiaowei Li (2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016)

PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping - Faqiang Sun; Huawei Li; Yinhe Han; Guihai Yan; Jun Ma (Seventh International Green and Sustainable Computing Conference, IGSC 2016, Hangzhou, China, November 7-9, 2016, 2016)

An ultra-low overhead LUT-based PUF for FPGA - Jiadong Wang; Aijiao Cui; Mengyang Li; Gang Qu; Huawei Li (2016 IEEE Asian Hardware-Oriented Security and Trust, AsianHOST 2016, Yilan, Taiwan, December 19-20, 2016, 2016)

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices - Ying Wang; Huawei Li; Xiaowei Li (Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD 2016, Austin, TX, USA, November 7-10, 2016, 2016)

A new countermeasure against scan-based side-channel attacks - Yanhui Luo; Aijiao Cui; Gang Qu; Huawei Li (IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, 2016)

An accurate algorithm for computing mutation coverage in model checking - Huina Chao; Huawei Li; Tiancheng Wang; Xiaowei Li; Bo Liu (2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016, 2016)

Path constraint solving based test generation for observability-enhanced branch coverage - Yanhong Zhou; Huawei Li; Tiancheng Wang; Bo Liu; Yingke Gao; Xiaowei Li (34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016, 2016)

An on-chip frequency programmable test clock generation and application method for small delay defect detection - Songwei Pei; Huawei Li; Song Jin; Jun Liu; Xiaowei Li (Integr., 2015)

Economizing TSV Resources in 3-D Network-on-Chip Design - Ying Wang; Yinhe Han; Lei Zhang; Binzhang Fu; Cheng Liu; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Data Remapping for Static NUCA in Degradable Chip Multiprocessors - Ying Wang; Lei Zhang; Yinhe Han; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing - Songwei Pei; Ye Geng; Huawei Li; Jun Liu; Song Jin (The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015, 2015)

A Lightweight Timing Channel Protection for Shared Memory Controllers - Guopei Liu; Ying Wang; Sen Li; Huawei Li; Xiaowei Li (24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015)

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs - Jun Zhou; Huawei Li; Tiancheng Wang; Sen Li; Ying Wang; Xiaowei Li (24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015)

TURO: A lightweight turn-guided routing scheme for 3D NoCs - Jun Zhou; Huawei Li; Tiancheng Wang; Ying Wang; Xiaowei Li (2015 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XVIII, Yokohama, Japan, April 13-15, 2015, 2015)

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory - Ying Wang; Yinhe Han; Cheng Wang; Huawei Li; Xiaowei Li (Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015)

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing - Ying Wang; Yinhe Han; Lei Zhang; Huawei Li; Xiaowei Li (Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015)

Temperature-aware software-based self-testing for delay faults - Ying Zhang; Zebo Peng; Jianhui Jiang; Huawei Li; Masahiro Fujita (Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015)

Retraining-based timing error mitigation for hardware neural networks - Jiachao Deng; Yuntan Fang; Zidong Du; Ying Wang; Huawei Li; Olivier Temam; Paolo Ienne; David Novo; Xiaowei Li; Yunji Chen; Chengyong Wu (Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015)

A case of precision-tunable STT-RAM memory design for approximate neural network - Ying Wang; Lili Song; Yinhe Han; Yuanqing Cheng; Huawei Li; Xiaowei Li (2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, 2015)

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans - Yun Cheng; Ying Wang; Huawei Li; Xiaowei Li (2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015, 2015)

On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island - Song Jin; Songwei Pei; Yinhe Han; Huawei Li (VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015, 2015)

Reinventing Memory System Design for Many-Accelerator Architecture - Ying Wang; Lei Zhang; Yinhe Han; Huawei Li (J. Comput. Sci. Technol., 2014)

Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach - Shuangde Fang; Zidong Du; Yuntan Fang; Yuanjie Huang; Yang Chen; Lieven Eeckhout; Olivier Temam; Huawei Li; Yunji Chen; Chengyong Wu (ACM Trans. Archit. Code Optim., 2014)

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels - Binzhang Fu; Yinhe Han; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications - Yuntan Fang; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Test-Quality Optimization for Variable n -Detections of Transition Faults - Dawen Xu; Huawei Li; Amirali Ghofrani; Kwang-Ting Cheng; Yinhe Han; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An On-Line Timing Error Detection Method for Silicon Debug - Yun Cheng; Huawei Li; Xiaowei Li (23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014, 2014)

A low power DRAM refresh control scheme for 3D memory cube - Ying Wang; Yinhe Han; Huawei Li (2014 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVII, Yokohama, Japan, April 14-16, 2014, 2014)

Functional test generation guided by steady-state probabilities of abstract design - Jian Wang; Huawei Li; Tao Lv; Tiancheng Wang; Xiaowei Li (Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014)

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube - Yinhe Han; Ying Wang; Huawei Li; Xiaowei Li (The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014, 2014)

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs - Jun Zhou; Huawei Li; Yuntan Fang; Tiancheng Wang; Yuanqing Cheng; Xiaowei Li (IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014, 2014)

A novel abstraction-guided simulation approach using posterior probabilities for verification - Jian Wang; Huawei Li; Xiaowei Li (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, April 28-30, 2014, 2014)

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction - Song Jin; Yinhe Han; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model - Zijian He; Tao Lv; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors - Ying Zhang; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Path Constraint Solving Based Test Generation for Hard-to-Reach States - Yanhong Zhou; Tiancheng Wang; Tao Lv; Huawei Li; Xiaowei Li (22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013)

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction - Yinhe Han; Ying Wang; Huawei Li; Xiaowei Li (2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, 2013)

RSAK: Random stream attack for phase change memory in video applications - Yuntan Fang; Huawei Li; Xiaowei Li (31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013)

Testable Path Selection and Grouping for Faster Than At-Speed Testing - Xiang Fu; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A High-Precision On-Chip Path Delay Measurement Architecture - Songwei Pei; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume - Songwei Pei; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2012)

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write - Yuntan Fang; Huawei Li; Xiaowei Li (21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012)

Statistical SDFC: A metric for evaluating test quality of small delay faults - Xuefeng Zhu; Huawei Li; Xiaowei Li (Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, April 23-25, 2012, 2012)

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip - Binzhang Fu; Yinhe Han; Huawei Li; Xiaowei Li (IEICE Trans. Inf. Syst., 2011)

Statistical lifetime reliability optimization considering joint effect of process variation and aging - Song Jin; Yinhe Han; Huawei Li; Xiaowei Li (Integr., 2011)

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects - Ying Zhang; Huawei Li; Yinghua Min; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects - Minjin Zhang; Huawei Li; Xiaowei Li (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications - Yuntan Fang; Huawei Li; Xiaowei Li (Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011)

Flex memory: Exploiting and managing abundant off-chip optical bandwidth - Ying Wang; Lei Zhang; Yinhe Han; Huawei Li; Xiaowei Li (Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011)

An abacus turn model for time/space-efficient reconfigurable routing - Binzhang Fu; Yinhe Han; Jun Ma; Huawei Li; Xiaowei Li (38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA, 2011)

A unified test architecture for on-line and off-line delay fault detections - Songwei Pei; Huawei Li; Xiaowei Li (29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, 2011)

Testable Critical Path Selection Considering Process Variation - Xiang Fu; Huawei Li; Xiaowei Li (IEICE Trans. Inf. Syst., 2010)

Graph partition based path selection for testing of small delay defects - Zijian He; Tao Lv; Huawei Li; Xiaowei Li (Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, 2010)

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing - Xiang Fu; Huawei Li; Xiaowei Li (Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010)

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework - Song Jin; Yinhe Han; Huawei Li; Xiaowei Li (Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010)

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths - Zijian He; Tao Lv; Huawei Li; Xiaowei Li (Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010)

Software-Based Self-Testing of Processors Using Expanded Instructions - Ying Zhang; Huawei Li; Xiaowei Li (Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010)

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs - Binzhang Fu; Yinhe Han; Huawei Li; Xiaowei Li (Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010)

An on-chip clock generation scheme for faster-than-at-speed delay testing - Songwei Pei; Huawei Li; Xiaowei Li (Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010)

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications - Huawei Li; Dawen Xu; Yinhe Han; Kwang-Ting Cheng; Xiaowei Li (2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, 2010)

On generation of a universal path candidate set containing testable long paths - Zijian He; Tao Lv; Huawei Li; Xiaowei Li (2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, 2010)

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors - Ying Wang; Lei Zhang; Yinhe Han; Huawei Li; Xiaowei Li (16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010, Tokyo, Japan, December 13-15, 2010, 2010)

Fast path selection for testing of small delay defects considering path correlations - Zijian He; Tao Lv; Huawei Li; Xiaowei Li (28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010)

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip - Ying Zhang; Huawei Li; Xiaowei Li (J. Comput. Sci. Technol., 2009)

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems - Lei Zhang; Yinhe Han; Qiang Xu; Xiaowei Li; Huawei Li (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Low Overhead On-Chip Path Delay Measurement Circuit - Songwei Pei; Huawei Li; Xiaowei Li (Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009)

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor - Zichu Qi; Hui Liu; Xiangku Li; Da Wang; Yinhe Han; Huawei Li; Weiwu Hu (Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009)

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay - Song Jin; Yinhe Han; Lei Zhang; Huawei Li; Xiaowei Li; Guihai Yan (Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009)

Impact of Hazards on Pattern Selection for Small Delay Defects - Jie Wang; Huawei Li; Yinghua Min; Xiaowei Li; Huaguo Liang (2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2009, Shanghai, China, 16-18 November 2009, 2009)

Small Delay Fault Simulation for Sequential Circuits - Li Liu; Jishun Kuang; Huawei Li (2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2009, Shanghai, China, 16-18 November 2009, 2009)

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan - Songwei Pei; Huawei Li; Xiaowei Li (2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2009, Shanghai, China, 16-18 November 2009, 2009)

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes - Binzhang Fu; Yinhe Han; Huawei Li; Xiaowei Li (2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2009, Shanghai, China, 16-18 November 2009, 2009)

Automatic Selection of Internal Observation Signals for Design Verification - Tao Lv; Huawei Li; Xiaowei Li (27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009)

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor - Da Wang; Yu Hu; Huawei Li; Xiaowei Li (J. Comput. Sci. Technol., 2008)

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults - Fei Wang; Yu Hu; Huawei Li; Xiaowei Li (Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, 2008)

Robust test generation for power supply noise induced path delay faults - Xiang Fu; Huawei Li; Yu Hu; Xiaowei Li (Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, 2008)

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance - Ying Zhang; Huawei Li; Xiaowei Li (17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, 2008)

A Case Study on At-Speed Testing for a Gigahertz Microprocessor - Da Wang; Rui Li; Yu Hu; Huawei Li; Xiaowei Li (4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, 2008)

Static Crosstalk Noise Analysis with Transition Map - Minjin Zhang; Huawei Li; Xiaowei Li (4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, 2008)

A Scan-Based Delay Test Method for Reduction of Overtesting - Hui Liu; Huawei Li; Yu Hu; Xiaowei Li (4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, 2008)

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects - Fei Wang; Yu Hu; Huawei Li; Xiaowei Li; Jing Ye; Yu Huang (2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008)

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects - Ying Zhang; Huawei Li; Xiaowei Li; Yu Hu (26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008)

Multiple Coupling Effects Oriented Path Delay Test Generation - Minjin Zhang; Huawei Li; Xiaowei Li (26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008)

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit - Yinhe Han; Yu Hu; Xiaowei Li; Huawei Li; Anshuman Chandra (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Routing Algorithm for Random Error Tolerance in Network-on-Chip - Lei Zhang; Huawei Li; Xiaowei Li (Human-Computer Interaction. HCI Applications and Services, 12th International Conference, HCI International 2007, Beijing, China, July 22-27, 2007, Proceedings, Part IV, 2007)

Bug analysis and corresponding error models in real designs - Tao Lv; Tong Xu; Yang Zhao; Huawei Li; Xiaowei Li (IEEE International High Level Design Validation and Test Workshop, HLDVT 2007, Irvine, CA, USA, November 7-9, 2007, 2007)

The design-for-testability features of a general purpose microprocessor - Da Wang; Xiaoxin Fan; Xiang Fu; Hui Liu; Ke Wen; Rui Li; Huawei Li; Yu Hu; Xiaowei Li (2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007, 2007)

Response compaction for system-on-a-chip based on advanced convolutional codes - Yinhe Han; Huawei Li; Xiaowei Li; Anshuman Chandra (Sci. China Ser. F Inf. Sci., 2006)

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time - Yu Hu; Yinhe Han; Xiaowei Li; Huawei Li; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2006)

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes - Yinhe Han; Xiaowei Li; Huawei Li; Anshuman Chandra (IEEE Trans. Instrum. Meas., 2006)

An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains - Tao Lv; Ling-Yi Liu; Yang Zhao; Huawei Li; Xiaowei Li (15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, 2006)

Fast Packet Classification using Group Bit Vector - Tong Liu; Huawei Li; Xiaowei Li; Yinhe Han (Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November - 1 December 2006, 2006)

Robust Test Generation for Precise Crosstalk-induced Path Delay Faults - Huawei Li; Pei-Fu Shen; Xiaowei Li (24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, 2006)

Selection of Crosstalk-Induced Faults in Enhanced Delay Test - Huawei Li; Xiaowei Li (J. Electron. Test., 2005)

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores - Yinhe Han; Yu Hu; Xiaowei Li; Huawei Li; Anshuman Chandra; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2005)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction - Yinhe Han; Xiaowei Li; Huawei Li; Anshuman Chandra (J. Comput. Sci. Technol., 2005)

An innovative free memory design for network processors in home network gateway - Shuguang Gong; Huawei Li; Xiaowei Li (IEEE Trans. Consumer Electron., 2005)

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code - Yinhe Han; Yu Hu; Huawei Li; Xiaowei Li (Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, 2005)

Design of an efficient memory subsystem for network processor - Shuguang Gong; Huawei Li; Yufeng Xu; Tong Liu; Xiaowei Li (Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, 2005)

Non-robust Test Generation for Crosstalk-Induced Delay Faults - Pei-Fu Shen; Huawei Li; Yong-Jun Xu; Xiaowei Li (14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005)

Using MUXs Network to Hide Bunches of Scan Chains - Yinhe Han; Yu Hu; Huawei Li; Xiaowei Li (6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, 2005)

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time - Yu Hu; Xiaowei Li; Huawei Li; Xiaoqing Wen (11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 12-14 December, 2005, Changsha, Hunan, China, 2005)

Rapid and Energy-Efficient Testing for Embedded Cores - Yinhe Han; Yu Hu; Huawei Li; Xiaowei Li; Anshuman Chandra (13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004)

Pair Balance-Based Test Scheduling for SOCs - Yu Hu; Yinhe Han; Huawei Li; Tao Lv; Xiaowei Li (13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004)

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes - Yinhe Han; Yu Hu; Huawei Li; Xiaowei Li; Anshuman Chandra (19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, 2004)

A Novel RT-Level Behavioral Description Based ATPG Method - Zhigang Yin; Yinghua Min; Xiaowei Li; Huawei Li (J. Comput. Sci. Technol., 2003)

Delay Test Pattern Generation Considering Crosstalk-Induced Effects - Huawei Li; Yue Zhang; Xiaowei Li (12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste - Yinhe Han; Yongjun Xu; Huawei Li; Xiaowei Li; Anshuman Chandra (12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003)

Clustering of behavioral phases in FSMs and its applications to VLSI test - Huawei Li; Yinghua Min; Zhongcheng Li (Sci. China Ser. F Inf. Sci., 2002)

Test Power Optimization Techniques for CMOS Circuits - Zuying Luo; Xiaowei Li; Huawei Li; Shiyuan Yang; Yinghua Min (11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002)

An RT-Level ATPG Based on Clustering of Circuit States - Huawei Li; Yinghua Min; Zhongcheng Li (10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001)

Reducing Power Dissipation during At-Speed Test Application - Xiaowei Li; Huawei Li; Yinghua Min (16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, 2001)

Reduction of Number of Paths to be Tested in Delay Testing - Huawei Li; Zhongcheng Li; Yinghua Min (J. Electron. Test., 2000)

Delay Testing with Double Observations - Huawei Li; Zhongcheng Li; Yinghua Min (7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998)