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Eric S. Fetzer
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2010 – 2019
- 2013
- [c2]Lalitha Mohana Kalyani-Garimella, Sri Raga Sudha Garimella, Kevin Duda, Eric S. Fetzer:
New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A. MWSCAS 2013: 1387-1390 - 2012
- [j4]Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley O. Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw:
A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers. IEEE J. Solid State Circuits 47(1): 177-193 (2012) - 2011
- [c1]Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski:
A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. ISSCC 2011: 84-86
2000 – 2009
- 2006
- [j3]Eric S. Fetzer:
Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design. IEEE Des. Test Comput. 23(6): 476-483 (2006) - [j2]Eric S. Fetzer, David M. Dahle, Casey Little, Kevin Safford:
The Parity protected, multithreaded register files on the 90-nm itanium microprocessor. IEEE J. Solid State Circuits 41(1): 246-255 (2006) - 2002
- [j1]Eric S. Fetzer, Mark Gibson, Anthony Klein, Naomi Calick, Chengyu Zhu, Eric Busta, Baker Mohammad
:
A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor. IEEE J. Solid State Circuits 37(11): 1433-1440 (2002)
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