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Suhaib A. Fahmy
Suhaib Ahmed Fahmy
Person information
- affiliation: King Abdullah University of Science and Technology, Saudi Arabia
- affiliation (former): University of Warwick, United Kingdom
- affiliation (former): Nanyang Technological University, Singapore
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2020 – today
- 2024
- [j41]I Nyoman Kusuma Wardana
, Julian W. Gardner
Collaborative Learning at the Edge for Air Pollution Prediction. IEEE Trans. Instrum. Meas. 73: 1-12 (2024) - [j40]Suhaib A. Fahmy, Jason D. Bakos:
Introduction to the Special Section on FPGA 2023. ACM Trans. Reconfigurable Technol. Syst. 17(3): 43:1-43:2 (2024) - [c94]Mohamed Bouaziz
Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design: (PhD Forum Paper). ASAP 2024: 204-205 - [c93]Hao Liu, Mohammed E. Fouda, Ahmed M. Eltawil, Suhaib A. Fahmy:
Split DNN Inference for Exploiting Near-Edge Accelerators. EDGE 2024: 84-91 - [c92]Mojtaba F. AlShams, Kamilya S. Smagulova, Suhaib A. Fahmy, Mohammed E. Fouda, Ahmed M. Eltawil:
DONNA: Distributed Optimized Neural Network Allocation on CIM-Based Heterogeneous Accelerators. EDGE 2024: 149-156 - [c91]Mohamed W. Hassan, Hatem Ltaief, Suhaib A. Fahmy:
High Throughput Massive MIMO Signal Decoding Using Multi-Level Tree Search on FPGAs. FCCM 2024: 13-23 - [c90]I Nyoman Kusuma Wardana, Suhaib A. Fahmy, Julian W. Gardner:
Low-Cost SCADA/HMI with Tiny Machine Learning for Monitoring Indoor CO2 Concentration. I2MTC 2024: 1-5 - [c89]Achref Rebai
SqueezeNIC: Low-Latency In-NIC Compression for Distributed Deep Learning. NAIC 2024: 61-68 - [i9]Inês Pinto Gouveia, Ahmad T. Sheikh, Ali Shoker, Suhaib A. Fahmy, Paulo Jorge Esteves Veríssimo:
Resilient and Secure Programmable System-on-Chip Accelerator Offload. CoRR abs/2406.18117 (2024) - [i8]Ahmad T. Sheikh, Ali Shoker, Suhaib A. Fahmy, Paulo Jorge Esteves Veríssimo:
ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips. CoRR abs/2409.02553 (2024) - 2023
- [j39]Lenos Ioannou
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs. ACM Trans. Reconfigurable Technol. Syst. 16(1): 8:1-8:26 (2023) - [j38]Alex R. Bucknall
ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge. ACM Trans. Reconfigurable Technol. Syst. 16(3): 34:1-34:33 (2023) - [c88]Ahmed M. Abdelmoniem
REFL: Resource-Efficient Federated Learning. EuroSys 2023: 215-232 - [c87]Ziyi Yang
Exploring FPGA Acceleration for Distributed Serverless Computing. FPL 2023: 345-346 - [c86]Edward Grindley, Thurstan Gray, James Wilkinson, Chris Vaux, Adam Ardron, Jack Deeley, Alexander Elliott, Nidhin Thandassery Sumithran
Introducing the NAIL Accelerator Interface Layer for Low Latency FPGA Offload. ICFPT 2023: 290-291 - [c85]Mohamed W. Hassan, Adel Dabah
Signal Detection for Large MIMO Systems Using Sphere Decoding on FPGAs. IPDPS 2023: 102-111 - 2022
- [j37]I Nyoman Kusuma Wardana
Estimation of missing air pollutant data using a spatiotemporal convolutional autoencoder. Neural Comput. Appl. 34(18): 16129-16154 (2022) - [j36]I Nyoman Kusuma Wardana
Correction to: Estimation of missing air pollutant data using a spatiotemporal convolutional autoencoder. Neural Comput. Appl. 34(18): 16155 (2022) - [j35]Abhishek Kumar Jain
Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. IEEE Trans. Parallel Distributed Syst. 33(6): 1478-1490 (2022) - [c84]Kamalakkannan Kamalavasan, Gihan R. Mudalige, István Z. Reguly, Suhaib A. Fahmy:
High throughput multidimensional tridiagonal system solvers on FPGAs. ICS 2022: 19:1-19:12 - [c83]Kamalakkannan Kamalavasan, Gihan R. Mudalige, István Z. Reguly, Suhaib A. Fahmy:
FPGA Acceleration of Structured-Mesh-Based Explicit and Implicit Numerical Solvers using SYCL. IWOCL 2022: 19:1-19:11 - [i7]Kamalakkannan Kamalavasan, István Z. Reguly, Suhaib A. Fahmy, Gihan R. Mudalige:
High Throughput Multidimensional Tridiagonal Systems Solvers on FPGAs. CoRR abs/2201.03950 (2022) - 2021
- [j34]I Nyoman Kusuma Wardana
Optimising Deep Learning at the Edge for Accurate Hourly Air Quality Prediction. Sensors 21(4): 1064 (2021) - [j33]Kalindu Herath
Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(12): 2508-2521 (2021) - [j32]Hua Yan, Shuang-Hua Yang, Yunfei Chen, Suhaib A. Fahmy:
Optimum Battery Weight for Maximizing Available Energy in UAV-Enabled Wireless Communications. IEEE Wirel. Commun. Lett. 10(7): 1410-1413 (2021) - [c82]Mansour Aldawood, Arshad Jhumka, Suhaib A. Fahmy:
Toward Secure VMs Allocation: Analysis of VMs Allocation Behaviours in the Cloud Computing Environments. CLOSER (Selected Papers) 2021: 25-46 - [c81]Mansour Aldawood, Arshad Jhumka, Suhaib A. Fahmy:
Sit Here: Placing Virtual Machines Securely in Cloud Environments. CLOSER 2021: 248-259 - [c80]Alex R. Bucknall, Suhaib A. Fahmy:
Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware. DATE 2021: 1616-1621 - [c79]Thinh Hung Pham, Shanker Shreejith
Heterogeneous Communication Virtualization for Distributed Embedded Applications. DSD 2021: 251-258 - [c78]Dean G. Chester, Taylor L. Groves, Simon D. Hammond, Tim Law, Steven A. Wright, Richard P. Smedley-Stevenson, Suhaib A. Fahmy, Gihan R. Mudalidge, Stephen A. Jarvis:
StressBench: A Configurable Full System Network and I/O Benchmark Framework. HPEC 2021 - [c77]Kamalakkannan Kamalavasan, Gihan R. Mudalige
High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers. IPDPS 2021: 1087-1096 - [i6]Kamalakkannan Kamalavasan, Gihan R. Mudalige, István Z. Reguly, Suhaib A. Fahmy:
High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers. CoRR abs/2101.01177 (2021) - [i5]Ahmed M. Abdelmoniem, Atal Narayan Sahu, Marco Canini
Resource-Efficient Federated Learning. CoRR abs/2111.01108 (2021) - 2020
- [j31]Ryan A. Cooke, Suhaib A. Fahmy:
A model for distributed in-network and near-edge computing with heterogeneous hardware. Future Gener. Comput. Syst. 105: 395-409 (2020) - [j30]Ryan A. Cooke
Exploring hardware accelerator offload for the Internet of Things. it Inf. Technol. 62(5-6): 207-214 (2020) - [j29]Lenos Ioannou
High Throughput Spatial Convolution Filters on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1392-1402 (2020) - [c76]Ryan A. Cooke, Suhaib A. Fahmy:
Quantifying the latency benefits of near-edge and in-network FPGA acceleration. EdgeSys@EuroSys 2020: 7-12 - [c75]Ryan A. Cooke, Suhaib A. Fahmy:
Characterizing Latency Overheads in the Deployment of FPGA Accelerators. FPL 2020: 347-352 - [c74]Alex R. Bucknall, Shanker Shreejith
Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq UltraScale+. FPT 2020: 215-220 - [c73]Xiangwei Li
High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j28]Stephen I. Roberts, Steven A. Wright
The Power-optimised Software Envelope. ACM Trans. Archit. Code Optim. 16(3): 21:1-21:27 (2019) - [c72]Lenos Ioannou
Network Intrusion Detection Using Neural Networks on FPGA SoCs. FPL 2019: 232-238 - [c71]Lenos Ioannou
Neural Network Overlay Using FPGA DSP Blocks. FPL 2019: 252-253 - [c70]Alex R. Bucknall, Shanker Shreejith
Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration. FPT 2019: 259-262 - [c69]Lenos Ioannou
Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration. FPT 2019: 355-358 - 2018
- [j27]Kizheppatt Vipin, Suhaib A. Fahmy
FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications. ACM Comput. Surv. 51(4): 72:1-72:39 (2018) - [j26]Shanker Shreejith
Smart Network Interfaces for Advanced Automotive Applications. IEEE Micro 38(2): 72-80 (2018) - [j25]Shanker Shreejith
Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1183-1191 (2018) - [c68]Suhaib A. Fahmy:
Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs. AHS 2018: 142-147 - [c67]Xiangwei Li
A time-multiplexed FPGA overlay with linear interconnect. DATE 2018: 1075-1080 - [c66]Shanker Shreejith
A Smart Network Interface Approach for Distributed Applications on Xilinx Zynq SoCs. FPL 2018: 186-190 - 2017
- [j24]Mikhail Asiatici
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5: 1900-1910 (2017) - [j23]Thinh Hung Pham
An End-to-End Multi-Standard OFDM Transceiver Architecture Using FPGA Partial Reconfiguration. IEEE Access 5: 21002-21015 (2017) - [j22]Rakesh Warrier, Shanker Shreejith
Fracturable DSP Block for Multi-context Reconfigurable Architectures. Circuits Syst. Signal Process. 36(7): 3020-3033 (2017) - [j21]Shanker Shreejith
VEGa: A High Performance Vehicular Ethernet Gateway on Hybrid FPGA. IEEE Trans. Computers 66(10): 1790-1803 (2017) - [j20]Bajaj Ronak
Multipumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1471-1482 (2017) - [j19]Philipp Mundhenk, Andrew Paverd
Security in Automotive Networks: Lightweight Authentication and Authorization. ACM Trans. Design Autom. Electr. Syst. 22(2): 25:1-25:27 (2017) - [c65]Ryan A. Cooke, Suhaib A. Fahmy:
In-network online data analytics with FPGAs. FPL 2017: 1-2 - [c64]Stephen I. Roberts, Steven A. Wright
Metrics for Energy-Aware Software Optimisation. ISC 2017: 413-430 - [i4]Philipp Mundhenk, Andrew Paverd, Artur Mrowca, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy, Samarjit Chakraborty:
Security in Automotive Networks: Lightweight Authentication and Authorization. CoRR abs/1703.03652 (2017) - [i3]Abhishek Kumar Jain
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays. CoRR abs/1705.02730 (2017) - [i2]Abdullah Al-Dujaili, Suhaib A. Fahmy:
High Throughput 2D Spatial Image Filters on FPGAs. CoRR abs/1710.05154 (2017) - 2016
- [j18]Thinh Hung Pham
Spectrally efficient emission mask shaping for OFDM cognitive radios. Digit. Signal Process. 50: 150-161 (2016) - [j17]Philipp Mundhenk, Artur Mrowca, Sebastian Steinhorst
Open source model and simulator for real-time performance analysis of automotive network security. SIGBED Rev. 13(3): 8-13 (2016) - [j16]Bajaj Ronak, Suhaib A. Fahmy:
Mapping for Maximum Performance on FPGA DSP Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 573-585 (2016) - [j15]Abhishek Ambede
Design and Realization of Variable Digital Filters for Software-Defined Radio Channelizers Using an Improved Coefficient Decimation Method. IEEE Trans. Circuits Syst. II Express Briefs 63-II(1): 59-63 (2016) - [j14]Thinh Hung Pham
Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1412-1420 (2016) - [c63]David Thomas, Suhaib A. Fahmy:
Message from the ASAP 2016 chairs. ASAP 2016: iii-iv - [c62]Abhishek Kumar Jain
Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? DASC/PiCom/DataCom/CyberSciTech 2016: 586-593 - [c61]Shanker Shreejith, Bezborah Anshuman, Suhaib A. Fahmy:
Accelerated Artificial Neural Networks on FPGA for fault detection in automotive systems. DATE 2016: 37-42 - [c60]Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Throughput oriented FPGA overlays using DSP blocks. DATE 2016: 1628-1633 - [c59]Abhishek Kumar Jain
DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. FCCM 2016: 1-8 - [c58]Bajaj Ronak, Suhaib A. Fahmy:
Initiation Interval Aware Resource Sharing for FPGA DSP Blocks. FCCM 2016: 135 - [c57]Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only). FPGA 2016: 278 - [c56]Mikhail Asiatici, Nithin George, Kizheppatt Vipin
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2 - [c55]Bajaj Ronak, Suhaib A. Fahmy:
Improved resource sharing for FPGA DSP blocks. FPL 2016: 1-4 - [c54]Malte Vesper, Dirk Koch, Kizheppatt Vipin
JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication. FPL 2016: 1-9 - [i1]Xiangwei Li, Abhishek Kumar Jain
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units. CoRR abs/1606.06460 (2016) - 2015
- [j13]Abhishek Kumar Jain, Xiangwei Li
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. SIGARCH Comput. Archit. News 43(4): 28-33 (2015) - [j12]Shanker Shreejith
Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems. IEEE Trans. Veh. Technol. 64(2): 453-465 (2015) - [c53]Kizheppatt Vipin
Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq. AHS 2015: 1-8 - [c52]Suhaib A. Fahmy, Kizheppatt Vipin
Virtualized FPGA Accelerators for Efficient Cloud Computing. CloudCom 2015: 430-435 - [c51]Shanker Shreejith
Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA. CrownCom 2015: 427-437 - [c50]Philipp Mundhenk, Sebastian Steinhorst
Security analysis of automotive architectures using probabilistic model checking. DAC 2015: 38:1-38:6 - [c49]Shanker Shreejith
Security aware network controllers for next generation automotive embedded systems. DAC 2015: 39:1-39:6 - [c48]Philipp Mundhenk, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy, Samarjit Chakraborty:
Lightweight authentication for secure automotive networks. DATE 2015: 285-288 - [c47]Abhishek Kumar Jain
Efficient Overlay Architecture Based on DSP Blocks. FCCM 2015: 25-28 - [c46]Hui Yan Cheah, Suhaib A. Fahmy, Nachiket Kapre:
On Data Forwarding in Deeply Pipelined Soft Processors. FPGA 2015: 181-189 - [c45]Bajaj Ronak, Suhaib A. Fahmy:
Minimizing DSP block usage through multi-pumping. FPT 2015: 184-187 - [c44]Liwei Yang, Magzhan Ikram, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
JIT trace-based verification for high-level synthesis. FPT 2015: 228-231 - 2014
- [j11]Thinh Hung Pham
Robust and Efficient OFDM Synchronization for FPGA-Based Radios. Circuits Syst. Signal Process. 33(8): 2475-2493 (2014) - [j10]Kizheppatt Vipin
ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq. IEEE Embed. Syst. Lett. 6(3): 41-44 (2014) - [j9]Hui Yan Cheah, Fredrik Brosser, Suhaib A. Fahmy
The iDEA DSP Block-Based Soft Processor for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(3): 19:1-19:23 (2014) - [j8]Abhishek Kumar Jain
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. J. Signal Process. Syst. 77(1-2): 61-76 (2014) - [c43]Kevin Shen-Hoong Ong, Suhaib A. Fahmy
A scalable and compact systolic architecture for linear solvers. ASAP 2014: 186-187 - [c42]Kizheppatt Vipin
Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs. CPSNA 2014: 31-36 - [c41]Bajaj Ronak, Suhaib A. Fahmy
Experiments in Mapping Expressions to DSP Blocks. FCCM 2014: 101 - [c40]Kizheppatt Vipin
Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq. FCCM 2014: 202-205 - [c39]Simin Xu, Suhaib A. Fahmy
Square-rich fixed point polynomial evaluation on FPGAs. FPGA 2014: 99-108 - [c38]Thinh Hung Pham
Efficient multi-standard cognitive radios on FPGAs. FPL 2014: 1-2 - [c37]Bajaj Ronak, Suhaib A. Fahmy
Efficient mapping of mathematical expressions into DSP blocks. FPL 2014: 1-4 - [c36]Kizheppatt Vipin
DyRACT: A partial reconfiguration enabled accelerator and test platform. FPL 2014: 1-7 - [c35]Hui Yan Cheah, Suhaib A. Fahmy
Analysis and optimization of a deeply pipelined FPGA soft processor. FPT 2014: 235-238 - [c34]Shanker Shreejith
Zero latency encryption with FPGAs for secure time-triggered automotive networks. FPT 2014: 256-259 - [c33]Martin Lukasiewycz, Shanker Shreejith
System simulation and optimization using reconfigurable hardware. ISIC 2014: 468-471 - [c32]Pilsoon Choi, Jason H. Gao, Nadesh Ramanathan, Mengda Mao, Shipeng Xu, Chirn Chye Boon
A case for leveraging 802.11p for direct phone-to-phone communications. ISLPED 2014: 207-212 - [c31]Thinh Hung Pham
Shaping Spectral Leakage for IEEE 802.11p Vehicular Communications. VTC Spring 2014: 1-5 - 2013
- [j7]Shanker Shreejith
Reconfigurable Computing in Next-Generation Automotive Networks. IEEE Embed. Syst. Lett. 5(1): 12-15 (2013) - [j6]Suhaib A. Fahmy
Architecture for Real-Time Nonparametric Probability Density Function Estimation. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 910-920 (2013) - [j5]Thinh Hung Pham
Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1549-1553 (2013) - [c30]Khoa Dang Pham, Abhishek Kumar Jain
Microkernel hypervisor for a hybrid ARM-FPGA platform. ASAP 2013: 219-226 - [c29]Martin Lukasiewycz, Sebastian Steinhorst
System architecture and software design for electric vehicles. DAC 2013: 95:1-95:6 - [c28]Shanker Shreejith
An approach for redundancy in FlexRay networks using FPGA partial reconfiguration. DATE 2013: 721-724 - [c27]Simin Xu, Suhaib A. Fahmy
Efficient Large Integer Squarers on FPGA. FCCM 2013: 198-201 - [c26]Kizheppatt Vipin
An Approach to a Fully Automated Partial Reconfiguration Design Flow. FCCM 2013: 231 - [c25]Fredrik Brosser, Hui Yan Cheah, Suhaib A. Fahmy
Iterative floating point computation using FPGA DSP blocks. FPL 2013: 1-6 - [c24]Shanker Shreejith
Accelerating validation of time-triggered automotive systems on FPGAs. FPT 2013: 4-11 - [c23]Kizheppatt Vipin
System-level FPGA device driver with high-level synthesis support. FPT 2013: 128-135 - [c22]Shanker Shreejith
Enhancing communication on automotive networks using data layer extensions. FPT 2013: 470-473 - [c21]Kizheppatt Vipin
Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems. IPDPS Workshops 2013: 172-181 - [c20]Karan R. Shetti, Suhaib A. Fahmy
Optimization of the HEFT Algorithm for a CPU-GPU Environment. PDCAT 2013: 212-218 - 2012
- [c19]Kizheppatt Vipin
Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration. ARC 2012: 13-25 - [c18]Samarjit Chakraborty, Martin Lukasiewycz, Christian Buckl
Embedded systems and software challenges in electric vehicles. DATE 2012: 424-429 - [c17]Hui Yan Cheah, Suhaib A. Fahmy
A lean FPGA soft processor built using a DSP block. FPGA 2012: 237-240 - [c16]Bajaj Ronak, Suhaib A. Fahmy
Evaluating the efficiency of DSP Block synthesis inference from flow graphs. FPL 2012: 727-730 - [c15]Kizheppatt Vipin
A high speed open source controller for FPGA Partial Reconfiguration. FPT 2012: 61-66 - [c14]Hui Yan Cheah, Suhaib A. Fahmy
iDEA: A DSP block based FPGA soft processor. FPT 2012: 151-158 - 2011
- [j4]Jorg Lotze, Suhaib A. Fahmy
A Model-Based Approach to Cognitive Radio Design. IEEE J. Sel. Areas Commun. 29(2): 455-468 (2011) - [c13]Kizheppatt Vipin
Enabling high level design of adaptive systems with partial reconfiguration. FPT 2011: 1-4 - [c12]Kizheppatt Vipin
A threat-based Connect6 implementation on FPGA. FPT 2011: 1-4 - [c11]Kizheppatt Vipin
Efficient region allocation for adaptive partial reconfiguration. FPT 2011: 1-6 - 2010
- [j3]Paul D. Sutton
Iris: an architecture for cognitive radio networking testbeds. IEEE Commun. Mag. 48(9): 114-122 (2010) - [c10]Suhaib A. Fahmy
Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing. ARC 2010: 343-350 - [c9]Paul D. Sutton
Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds. CrownCom 2010: 1-5 - [c8]Suhaib A. Fahmy
Histogram-based probability density function estimation on FPGAs. FPT 2010: 449-453
2000 – 2009
- 2009
- [j2]Suhaib A. Fahmy
High-throughput one-dimensional median and weighted median filters on FPGA. IET Comput. Digit. Tech. 3(4): 384-394 (2009) - [c7]Suhaib A. Fahmy
Generic Software Framework for Adaptive Applications on FPGAs. FCCM 2009: 55-62 - [c6]Jorg Lotze, Suhaib A. Fahmy
Development Framework for Implementing FPGA-Based Cognitive Network Nodes. GLOBECOM 2009: 1-7 - 2008
- [b1]Suhaib Ahmed Fahmy:
Hardware acceleration of the trace transform for vision applications. Imperial College London, UK, 2008 - [c5]Suhaib A. Fahmy
Generalised Parallel Bilinear Interpolation Architecture for Vision Systems. ReConFig 2008: 331-336 - 2007
- [j1]Suhaib A. Fahmy
Real-time hardware acceleration of the trace transform. J. Real Time Image Process. 2(4): 235-248 (2007) - 2006
- [c4]Suhaib A. Fahmy
Investigating Trace Transform Architectures for Face Authentication. FPL 2006: 1-2 - [c3]Suhaib A. Fahmy
Efficient Realtime FPGA Implementation of the Trace Transform. FPL 2006: 1-6 - 2005
- [c2]Suhaib A. Fahmy
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. DATE 2005: 8-13 - [c1]Suhaib A. Fahmy
Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. FPL 2005: 142-147
Coauthor Index
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