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Brian C. Richards
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2020 – today
- 2023
- [c17]Sohum Datta, Brian C. Richards, Harrison Liew
, Youbin Kim, Daniel Sun, Jan M. Rabaey:
HDBinaryCore: A 28nm 2048-bit Hyper-Dimensional biosignal classifier achieving 25 nJ/prediction for EMG hand-gesture recognition. ESSCIRC 2023: 229-232 - 2022
- [j7]Colin Schmidt
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. IEEE J. Solid State Circuits 57(1): 140-152 (2022) - 2021
- [c16]Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. ISSCC 2021: 58-60
2010 – 2019
- 2019
- [j6]Steven Bailey
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits 54(10): 2786-2801 (2019) - 2018
- [c15]Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC 2018: 285-288 - 2017
- [c14]Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn
A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET. A-SSCC 2017: 305-308 - 2016
- [j5]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4): 930-942 (2016) - [j4]Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
An Agile Approach to Building RISC-V Microprocessors. IEEE Micro 36(2): 8-20 (2016) - 2015
- [c13]Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium 2015: 1-45 - [c12]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC 2015: 316- - 2012
- [c11]Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic:
Chisel: constructing hardware in a Scala embedded language. DAC 2012: 1216-1225 - 2011
- [j3]Ji-Hoon Park, Brian C. Richards, Borivoje Nikolic
A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band. IEEE J. Solid State Circuits 46(11): 2524-2534 (2011)
2000 – 2009
- 2009
- [c10]Brian C. Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic
A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. CICC 2009: 499-502 - 2007
- [c9]Dejan Markovic, Chen Chang, Brian C. Richards, Hayden Kwok-Hay So
ASIC Design and Verification in an FPGA Environment. CICC 2007: 737-740 - 2004
- [c8]Kimmo Kuusilinna, Chen Chang, Hans-Martin Blüthgen, Danijela Cabric, Brian C. Richards, Robert W. Brodersen:
Describing MIMO designs for rapid prototyping in the BEE environment. EUSIPCO 2004: 693-696 - 2003
- [j2]Kimmo Kuusilinna, Chen Chang, M. Josephine Ammer, Brian C. Richards, Robert W. Brodersen:
Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications. EURASIP J. Adv. Signal Process. 2003(6): 502-513 (2003) - [c7]Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Robert W. Brodersen:
Implementation of BEE: a real-time large-scale hardware emulation engine. FPGA 2003: 91-99 - [c6]Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Allen Chen, Nathan Chan, Robert W. Brodersen, Borivoje Nikolic
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment. IEEE International Workshop on Rapid System Prototyping 2003: 148-
1990 – 1999
- 1995
- [c5]Allan Christian Long Jr., Shankar Narayanaswamy, Andrew J. Burstein, Richard Han, Ken Lutz, Brian C. Richards, Samuel Sheng, Robert W. Brodersen, Jan M. Rabaey:
A prototype user interface for a mobile multimedia terminal. CHI 95 Conference Companion 1995: 81-82 - [c4]Eric A. Brewer
Design of Wireless Portable Systems. COMPCON 1995: 169-176 - 1994
- [c3]Robert W. Brodersen, Thomas D. Burd, Fred L. Burghardt, Andrew J. Burstein, Anantha P. Chandrakasan, Roger Doering, Shankar Narayanaswamy, Trevor Pering, Brian C. Richards, Thomas E. Truman, Jan M. Rabaey:
Research challenges in wireless multimedia. PIMRC 1994: 1-5 - 1991
- [j1]C. Bernard Shung, Rajeev Jain, Ken Rimey, Edward Wang, Mani B. Srivastava, Brian C. Richards, Erik Lettang, Syed Khalid Azim, Lars E. Thon, Paul N. Hilfinger, Jan M. Rabaey, Robert W. Brodersen:
An integrated CAD system for algorithm-specific IC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 447-463 (1991) - 1990
- [c2]Mitch Weintraub, G. Chen, J. Mankoski, Hy Murveit, A. Stölzle, Shankar Narayanaswamy, P. Schrupp, Brian C. Richards, Jan M. Rabaey, Robert W. Brodersen:
Hardware for Hidden Markov-Model-Based, Large-Vocabulary Real-Time Speech Recognition. HLT 1990
1980 – 1989
- 1987
- [c1]Brian C. Richards, Alex Sherstinsky, Robert W. Brodersen:
A parameterized VLSI video-rate histogram processor. ICASSP 1987: 491-494
Coauthor Index
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